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m68hc08 microcontrollers freescale.com mc68hc908qb8 MC68HC908QB4 mc68hc908qy8 data sheet mc68hc908qb8 rev. 1 6/3/2005

mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc., 2005. all rights reserved. mc68hc908qb8 MC68HC908QB4 mc68hc908qy8 data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) june 3, 2005 1 initial full release n/a
revision history mc68hc908qb8 data sheet, rev. 1 4 freescale semiconductor
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 5 list of chapters chapter 1 general descr iption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 chapter 2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 chapter 3 analog-to-digital converter (adc10) module . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 chapter 4 auto wakeup module (awu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 chapter 5 configuration regist er (config) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 chapter 6 computer operating properly (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 chapter 7 central processor unit (cpu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 chapter 8 external interrupt (i rq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 chapter 9 keyboard interrupt module (kbi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 chapter 10 low-voltage inhi bit (lvi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 chapter 11 oscillator module (osc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 chapter 12 input/output ports (p orts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 chapter 13 enhanced serial commun ications interface (esci) modu le . . . . . . . . . . . . . 109 chapter 14 system integration module (sim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 chapter 15 serial peripheral interface (spi) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 chapter 16 timer interface modul e (tim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 chapter 17 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 chapter 18 electrical spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 chapter 19 ordering information and mechanical specifications . . . . . . . . . . . . . . . . . . 227
list of chapters mc68hc908qb8 data sheet, rev. 1 6 freescale semiconductor
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 7 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.6 pin function priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 chapter 2 memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4 direct page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.5 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.6 flash memory (flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.6.1 flash control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.6.2 flash page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.6.3 flash mass erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6.4 flash program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6.5 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.6.6 flash block protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 chapter 3 analog-to-digital c onverter (adc10) module 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3.1 clock select and divide circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.2 input select and pin control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3 conversion control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3.1 initiating conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3.2 completing conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3.3 aborting conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3.4 total conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
table of contents mc68hc908qb8 data sheet, rev. 1 8 freescale semiconductor 3.3.4 sources of error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.4.1 sampling error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.4.2 pin leakage error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.4.3 noise-induced errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.4.4 code width and quantization error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3.4.5 linearity errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3.4.6 code jitter, non-monotonicity and missing codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.6 adc10 during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.7.1 adc10 analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.7.2 adc10 analog ground pin (v ssa ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.7.3 adc10 voltage reference high pin (v refh ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.7.4 adc10 voltage reference low pin (v refl ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.7.5 adc10 channel pins (adn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.8.1 adc10 status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.8.2 adc10 result high register (adrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.8.3 adc10 result low register (adrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.8.4 adc10 clock register (adclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 chapter 4 auto wakeup module (awu) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6.1 port a i/o register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6.2 keyboard status and control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.6.3 keyboard interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.6.4 configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.6.5 configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 9 chapter 5 configuration register (config) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 chapter 6 computer operatin g properly (cop) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.1 busclkx4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.5 internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.6 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.7 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.5 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.7 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 6.8 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 chapter 7 central processor unit (cpu) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
table of contents mc68hc908qb8 data sheet, rev. 1 10 freescale semiconductor chapter 8 external interrupt (irq) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.3.1 mode = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.3.2 mode = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.7.1 irq input pins (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 chapter 9 keyboard interrupt module (kbi) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.3.1 keyboard operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.3.1.1 modek = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.3.1.2 modek = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 9.3.2 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.6 kbi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.7.1 kbi input pins (kbix:kbi0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.8.1 keyboard status and control register (kbscr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.8.2 keyboard interrupt enable register (kbier). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.8.3 keyboard interrupt polarity register (kbipr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 chapter 10 low-voltage inhibit (lvi) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.3.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.3.2 forced reset operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 11 10.3.3 lvi hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.3.4 lvi trip selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.4 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.6 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 chapter 11 oscillator module (osc) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3.1 internal signal definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.1.1 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.1.2 xtal oscillator clock (xtalclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.1.3 rc oscillator clock (rcclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.1.4 internal oscillator clock (intclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 11.3.1.5 bus clock times 4 (busclkx4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.1.6 bus clock times 2 (busclkx2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.2 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.2.1 internal oscillator trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.3.2.2 internal to external clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 11.3.2.3 external to internal clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 11.3.3 external oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.3.4 xtal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.3.5 rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.6 osc during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.7.1 oscillator input pin (osc1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.7.2 oscillator output pin (osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.8.1 oscillator status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.8.2 oscillator trim register (osctrim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 chapter 12 input/output ports (ports) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.2.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.2.2 data direction register a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
table of contents mc68hc908qb8 data sheet, rev. 1 12 freescale semiconductor 12.2.3 port a input pullup enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 12.2.4 port a summary table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.2 data direction register b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.3.3 port b input pullup enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 12.3.4 port b summary table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 chapter 13 enhanced serial communications interface (esci) module 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 13.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 13.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 13.3.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 13.3.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 13.3.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.3.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.3.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.3.2.4 idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.3.2.5 inversion of transmitted output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 13.3.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.3.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.3.3.2 character reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.3.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 13.3.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.3.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.3.3.6 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.4.1 transmitter interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 13.4.2 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 13.4.3 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 13.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 13.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 13.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.6 esci during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.7.1 esci transmit data (txd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.7.2 esci receive data (rxd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.8.1 esci control register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.8.2 esci control register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.8.3 esci control register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.8.4 esci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.8.5 esci status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 13.8.6 esci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 13 13.8.7 esci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13.8.8 esci prescaler register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.9 esci arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13.9.1 esci arbiter control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13.9.2 esci arbiter data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.9.3 bit time measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.9.4 arbitration mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 chapter 14 system integrati on module (sim) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 14.2 rst and irq pins initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 14.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 14.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 14.3.2 clock start-up from por. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 14.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 14.4 reset and system initializat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 14.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 14.4.2 active resets from intern al sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 14.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 14.4.2.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 14.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 14.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 44 14.5 sim counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14.5.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14.5.2 sim counter during stop mode recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14.5.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 14.6 exception control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 14.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 14.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 14.6.1.2 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.6.2 interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.6.2.1 interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.6.2.2 interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.6.2.3 interrupt status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 14.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 14.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 14.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 14.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 14.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14.8.1 sim reset status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14.8.2 break flag control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
table of contents mc68hc908qb8 data sheet, rev. 1 14 freescale semiconductor chapter 15 serial peripheral interface (spi) module 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 15.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 15.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 15.3.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 15.3.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 15.3.3 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15.3.3.1 clock phase and polarity controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15.3.3.2 transmission format when cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15.3.3.3 transmission format when cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 15.3.3.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 61 15.3.4 queuing transmission data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15.3.5 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15.3.6 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15.3.6.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15.3.6.2 mode fault error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 15.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.6 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.7.1 miso (master in/slave out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.7.2 mosi (master out/slave in). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.7.3 spsck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.7.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 15.8.1 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.8.2 spi status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 72 15.8.3 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 chapter 16 timer interface module (tim) 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 16.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 16.3.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 16.3.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 16.3.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 16.3.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 16.3.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 78 16.3.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.3.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.3.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 16.3.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 15 16.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.6 tim during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.7.1 tim channel i/o pins (tch3:tch0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.7.2 tim clock pin (tclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.8.1 tim status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 83 16.8.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 16.8.3 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 16.8.4 tim channel status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 16.8.5 tim channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 chapter 17 development support 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 17.2 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 17.2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 17.2.1.1 flag protection during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 17.2.1.2 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 17.2.1.3 cop during break in terrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 93 17.2.2 break module registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 17.2.2.1 break status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 17.2.2.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 17.2.2.3 break auxiliary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 17.2.2.4 break status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 17.2.2.5 break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 17.2.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 17.3 monitor module (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 17.3.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 17.3.1.1 normal monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 17.3.1.2 forced monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.3.1.3 monitor vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.3.1.4 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 17.3.1.5 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 17.3.1.6 baud rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 17.3.1.7 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 17.3.2 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 chapter 18 electrical specifications 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 18.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 18.3 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
table of contents mc68hc908qb8 data sheet, rev. 1 16 freescale semiconductor 18.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 18.5 5-v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 18.6 typical 5-v output drive characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 10 18.7 5-v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 18.8 3-v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 18.9 typical 3-v output drive characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 13 18.10 3-v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 18.11 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 18.12 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 18.13 adc10 characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 18.14 5.0-volt spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 18.15 3.0-volt spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 18.16 timer interface module characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 18.17 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 chapter 19 ordering information and m echanical specifications 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 19.2 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 19.3 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 17 chapter 1 general description 1.1 introduction the mc68hc908qb8 is a member of the low-cost , high-performance m68hc08 family of 8-bit microcontroller units (mcus). all mcus in the fa mily use the enhanced m68hc 08 central processor unit (cpu08) and are available with a variety of mo dules, memory sizes and types, and package types. 0.4 1.2 features features include: high-performance m68hc08 cpu core fully upward-compatible object code with m68hc05 family 5-v and 3-v operating voltages (v dd ) 8-mhz internal bus operation at 5 v, 4-mhz at 3 v trimmable internal oscillator ? software selectable 1 mhz, 2 mhz, or 3.2 mhz internal bus operation ? 8-bit trim capability ? 25% untrimmed ? trimmable to approximately 0.4% (1) software selectable crystal oscillator range, 32?100 khz, 1?8 mhz, and 8?32 mhz software configurable input clock from either internal or external source auto wakeup from stop capability using dedica ted internal 32-khz rc or bus clock source on-chip in-application programmable flash memory ? internal program/erase voltage generation ? monitor rom containing user callable program/erase routines ? flash security (2) table 1-1. summary of device variations device flash/ram memory size adc 16-bit timer channels esci spi pin count mc68hc908qb8 8k/256 bytes 10 channel, 10 bit 4 yes yes 16 pins MC68HC908QB4 4k/128 bytes 10 channel, 10 bit 4 yes yes 16 pins mc68hc908qy8 8k/256 bytes 4 channel, 10 bit 2 no no 16 pins 1. see 18.11 oscillator characteristics for internal oscillator specifications 2. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users.
general description mc68hc908qb8 data sheet, rev. 1 18 freescale semiconductor on-chip random-acc ess memory (ram) enhanced serial communicati ons interface (esci) module serial peripheral interface (spi) module 4-channel, 16-bit timer interface (tim) module 10-channel, 10-bit analog-to-digital converter (adc) with internal bandgap reference channel (adc10) up to 13 bidirectional input/output (i/o) lines and one input only: ? six shared with kbi ? ten shared with adc ? four shared with tim ? two shared with esci ? four shared with spi ? one input only shared with irq ? high current sink/source capability on all port pins ? selectable pullups on all ports, selectable on an individual bit basis ? three-state ability on all port pins 6-bit keyboard interrupt with wakeup feature (kbi) ? programmable for rising/falling or high/low level detect low-voltage inhibit (lvi) module features: ? software selectable trip point system protection features: ? computer operating properly (cop) watchdog ? low-voltage detection with reset ? illegal opcode detection with reset ? illegal address detection with reset external asynchronous interrupt pin with internal pullup (irq ) shared with general-purpose input pin master asynchronous reset pin with internal pullup (rst ) shared with general-purpose input/output (i/o) pin memory mapped i/o registers power saving stop and wait modes mc68hc908qb8, MC68HC908QB4 and mc68hc90 8qy8 are available in these packages: ? 16-pin plastic dual in-line package (pdip) ? 16-pin small outline integrated circuit (soic) package ? 16-pin thin shrink small outline packages (tssop) features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications efficient c language support
mcu block diagram mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 19 1.3 mcu block diagram figure 1-1 shows the structure of the mc68hc908qb8. figure 1-1. block diagram rst , irq : pins have internal pull up device all port pins have programmable pull up device pta[0:5]: higher current sink and source capability pta0/tch0/ad0/kbi0 pta1/tch1/ad1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 4-channel 16-bit timer module keyboard interrupt module single interrupt module auto wakeup low-voltage inhibit cop module 10-channel 10-bit adc enhanced serial ptb0/spsck/ad4 ptb ddrb m68hc08 cpu pta ddra ptb1/mosi/ad5 ptb2/miso/ad6 ptb3/ss /ad7 ptb4/rxd/ad8 ptb5/txd/ad9 ptb6/tch2 ptb7/tch3 mc68hc908qb8 power supply v dd v ss clock generator communications interface module module serial peripheral interface 8192 bytes user flash 256 bytes user ram monitor rom mc68hc908qb8 break module development support
general description mc68hc908qb8 data sheet, rev. 1 20 freescale semiconductor 1.4 pin assignments the mc68hc908qb8, MC68HC908QB4, and mc68hc 908qy8 are available in 16-pin packages. figure 1-2 shows the pin assignment for these packages. figure 1-2. mcu pin assignments 1.5 pin functions table 1-2 provides a description of the pin functions. 1 2 3 4 5 6 7 8 ptb0 ptb2 ptb3 ptb4 ptb6 ptb7 ptb1 16-pin assignment mc68hc908qy8 pdip/soic v dd pta1/tch1/ad1/kbi1 ptb5 pta2/irq /kbi2/tclk pta0/tch0/ad0/kbi0 pta5/osc1/ad3/kbi5 pta4/osc2/ad2/kbi4 pta3/rst /kbi3 16 15 14 13 12 11 10 9 v ss 1 2 3 4 5 6 7 8 ptb0/sck/ad4 ptb2/miso/ad6 ptb3/ss /ad7 ptb4/rx/ad8 ptb6/tch2 ptb7/tch3 ptb1/mosi/ad5 16-pin assignment mc68hc908qb8/MC68HC908QB4 pdip/soic v dd pta1/tch1/ad1/kbi1 ptb5/tx/ad9 pta2/irq /kbi2/tclk pta0/tch0/ad0/kbi0 pta5/osc1/ad3/kbi5 pta4/osc2/ad2/kbi4 pta3/rst /kbi3 16 15 14 13 12 11 10 9 v ss ptb2 ptb4 ptb5 ptb6 ptb0 ptb1 ptb3 16-pin assignment mc68hc908qy8 tssop pta0/tch0/ad0/kbi0 pta3/rst /kbi3 ptb7 pta4/osc2/ad2/kbi4 pta2/irq /kbi2/tclk v ss v dd pta5/osc1/ad3/kbi5 pta1/tch1/ad1/kbi1 ptb2/miso/ad6 ptb4//rx/ad8 ptb5/tx/ad9 ptb6/tch2 ptb0/sck/ad4 ptb1/mosi/ad5 ptb3/ss /ad7 16-pin assignment mc68hc908qb8/MC68HC908QB4 tssop pta0/tch0/ad0/kbi0 pta3/rst /kbi3 ptb7/tch3 pta4/osc2/ad2/kbi4 pta2/irq /kbi2/tclk v ss v dd pta5/osc1/ad3/kbi5 pta1/tch1/ad1/kbi1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
pin functions mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 21 table 1-2. pin functions pin name description input/output v dd power supply power v ss power supply ground power pta0 pta0 ? general purpose i/o port input/output tch0 ? timer channel 0 i/o input/output ad0 ? a/d channel 0 input input kbi0 ? keyboard interrupt input 0 input pta1 pta1 ? general purpose i/o port input/output tch1 ? timer channel 1 i/o input/output ad1 ? a/d channel 1 input input kbi1 ? keyboard interrupt input 1 input pta2 pta2 ? general purpose input-only port input irq ? external interrupt with programmable pullup and schmitt trigger input input kbi2 ? keyboard interrupt input 2 input tclk ? timer clock input input pta3 pta3 ? general purpose i/o port input/output rst ? reset input, active low with internal pullup and schmitt trigger input kbi3 ? keyboard interrupt input 3 input pta4 pta4 ? general purpose i/o port input/output osc2 ?xtal oscillator output (xtal option only) rc or internal oscillator output (osc2en = 1 in ptapue register) output output ad2 ? a/d channel 2 input input kbi4 ? keyboard interrupt input 4 input pta5 pta5 ? general purpose i/o port input/output osc1 ? xtal, rc, or external oscillator input input ad3 ? a/d channel 3 input input kbi5 ? keyboard interrupt input 5 input ptb0 ptb0 ? general-purpose i/o port input/output spsck ? spi serial clock input/output ad4 ? a/d channel 4 input input ptb1 ptb1 ? general-purpose i/o port input/output mosi ? spi master out slave in input/output ad5 ? a/d channel 5 input input ptb2 ptb2 ? general-purpose i/o port input/output miso ? spi master in slave out input/output ad6 ? a/d channel 6 input input ptb3 ptb3 ? general-purpose i/o port input/output ss ? spi slave select input ad7 ? a/d channel 7 input input ? continued on next page
general description mc68hc908qb8 data sheet, rev. 1 22 freescale semiconductor 1.6 pin function priority table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin. note upon reset all pins come up as input ports regardless of the priority table. ptb4 ptb4 ? general-purpose i/o port input/output rxd ? esci receive data i/o input/output ad8 ? a/d channel 8 input input ptb5 ptb5 ? general-purpose i/o port input/output txd ? esci transmit data i/o output ad9 ? a/d channel 9 input input ptb6 ptb6 ? general-purpose i/o port input/output tch2 ? timer channel 2 i/o input/output ptb7 ptb7 ? general-purpose i/o port input/output tch3 ? timer channel 3 i/o input/output table 1-3. function priority in shared pins pin name highest-to-lowest priority sequence pta0 (1) 1. when a pin is to be used as an adc pi n, the i/o port function should be left as an input and all other shared modules should be disabled. the adc does not override additional modules using the pin. ad0 tch0 kbi0 pta0 pta1 (1) ad1 tch1 kbi1 pta1 pta2 irq tclk kbi2 pta2 pta3 rst kbi3 pta3 pta4 (1) osc2 ad2 kbi4 pta4 pta5 (1) osc1 ad3 kbi5 pta5 ptb0 (1) ad4 spsck ptb0 ptb1 (1) ad5 mosi ptb1 ptb2 (1) ad6 miso ptb2 ptb3 (1) ad7 ss ptb3 ptb4 (1) ad8 rxd ptb4 ptb5 (1) ad9 txd ptb5 ptb6 tch2 ptb6 ptb7 tch3 ptb7 table 1-2. pin functions (continued) pin name description input/output
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 23 chapter 2 memory 2.1 introduction the central processor unit (cpu08) can address 64 kb ytes of memory space. the memory map, shown in figure 2-1 . 2.2 unimplemented memory locations executing code from an unimplemented locati on will cause an illegal address reset. in figure 2-1 , unimplemented locations are shaded. 2.3 reserved memory locations accessing a reserved location can have unpr edictable effects on mcu operation. in figure 2-1 , register locations are marked with the word reserved or with the letter r. 2.4 direct page registers figure 2-2 shows the memory mapped registers of the mc68hc908qb8. registers with addresses between $0000 and $00ff are considered direct page regi sters and all instructions including those with direct page addressing modes can access them. r egisters between $0100 and $ffff require non-direct page addressing modes. see chapter 7 central processor unit (cpu) for more information on addressing modes.
memory mc68hc908qb8 data sheet, rev. 1 24 freescale semiconductor $0000 $003f idirect page registers 64 bytes $0040 $013f ram 256 bytes reserved 64 bytes $0040 $007f $0140 $27ff unimplemented 9920 bytes ram 128 bytes $0080 $00ff $2800 $2a1f auxiliary rom 544 bytes reserved 64 bytes $0100 $013f $2a20 $2f7d unimplemented 1374 bytes $2f7e $2fff auxiliary rom 130 bytes $3000 $ddff unimplemented 44,544 bytes $de00 $fdff flash memory 8192 bytes reserved 4096 bytes $de00 $edff $fe00 $fe1f miscellaneous registers 32 bytes flash memory 4096 bytes $ee00 $fdff $fe20 $ff7d monitor rom 350 bytes $ff7e $ffaf unimplemented 50bytes $ffb0 $ffbd flash 14 bytes $ffbe $ffc1 miscellaneous registers 4 bytes $ffc2 $ffcf flash 14 bytes $ffd0 $ffff user vectors 48 bytes mc68hc908qb8 and mc68hc908qy8 memory map MC68HC908QB4 memory map figure 2-1. memory map
direct page registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 25 addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 104. read: r awul pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 106. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 $0003 reserved $0004 data direction register a (ddra) see page 104. read: r r ddra5 ddra4 ddra3 0 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 107. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 $000a reserved $000b port a input pullup enable register (ptapue) see page 105. read: osc2en 0 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 $000c port b input pullup enable register (ptbpue) see page 108. read: ptbpue7 ptbpue6 ptbpue5 ptbpue4 ptbpue3 ptbpue2 ptbpue1 ptbpue0 write: reset:00000000 $000d spi control register (spcr) see page 171. read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 $000e spi status and control register (spscr) see page 172. read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 $000f spi data register (spdr) see page 174. read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0010 esci control register 1 (scc1) see page 122. read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $0011 esci control register 2 (scc2) see page 124. read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0012 esci control register 3 (scc3) see page 125. read: r8 t8 r r orie neie feie peie write: reset:u0000000 $0013 esci status register 1 (scs1) see page 126. read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 1 of 5)
memory mc68hc908qb8 data sheet, rev. 1 26 freescale semiconductor $0014 esci status register 2 (scs2) see page 129. read:000000bkfrpf write: reset:00000000 $0015 esci data register (scdr) see page 129. read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0016 esci baud rate register (scbr) see page 130. read: lint linr scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 $0017 esci prescaler register (scpsc) see page 131. read: pds2 pds1 pds0 pssb4 pssb3 pssb2 pssb1 pssb0 write: reset:00000000 $0018 esci arbiter control register (sciactl) see page 135. read: am1 alost am0 aclk afin arun arovfl ard8 write: reset:00000000 $0019 esci arbiter data register (sciadat) see page 136. read: ard7 ard6 ard5 ard4 ard3 ard2 ard1 ard0 write: reset:00000000 $001a keyboard status and control register (kbscr) see page 87. read: 0 0 0 0 keyf 0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (kbier) see page 88. read: 0 awuie kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $001c keyboard interrupt polarity register (kbipr) see page 88. read: 0 0 kbip5 kbip4 kbip3 kbip2 kbip1 kbip0 write: reset:00000000 $001d irq status and control register (intscr) see page 81. read: 0 0 0 0 irqf 0 imask mode write: ack reset:00000000 $001e configuration register 2 (config2) (1) see page 57. read: irqpud irqen rrr escibdsrc oscenin- stop rsten write: reset:00000000 (2) 1. one-time writable register after each reset. 2. rsten reset to 0 by a power-on reset (por) only. $001f configuration register 1 (config1) (1) see page 58. read: coprs lvistop lvirstd lvipwrd lvitrip ssrec stop copd write: reset:00000 (2) 000 1. one-time writable register after each reset. 2. lvitrip reset to 0 by a power-on reset (por) only. $0020 tim status and control register (tsc) see page 183. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 tim counter register high (tcnth) see page 185. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 2 of 5)
direct page registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 27 $0022 tim counter register low (tcntl) see page 185. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 $0023 tim counter modulo register high (tmodh) see page 185. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 $0024 tim counter modulo register low (tmodl) see page 185. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:11111111 $0025 tim channel 0 status and control register (tsc0) see page 186. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 tim channel 0 register high (tch0h) see page 189. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $0027 tim channel 0 register low (tch0l) see page 189. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $0028 tim channel 1 status and control register (tsc1) see page 186. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 tim channel 1 register high (tch1h) see page 189. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $002a tim channel 1 register low (tch1l) see page 189. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $002b $002f reserved $0030 tim channel 2 status and control register (tsc2) see page 186. read: ch2f ch2ie 0 ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 $0031 tim channel 2 register high (tch2h) see page 189. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $0032 tim channel 2 register low (tch2l) see page 189. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $0033 tim channel 3 status and control register (tsc3) see page 186. read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset:00000000 $0034 tim channel 3 register high (tch3h) see page 189. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset $0035 tim channel 3 register low (tch3l) see page 189. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 3 of 5)
memory mc68hc908qb8 data sheet, rev. 1 28 freescale semiconductor $0036 oscillator status and control register (oscsc) see page 100. read: oscopt1 oscopt0 icfs1 icfs0 ecfs1 ecfs0 ecgon ecgst write: reset:00000000 $0037 reserved $0038 oscillator trim register (osctrim) see page 101. read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 $0039 $003b reserved $003c adc10 status and control register (adscr) see page 46. read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $003d adc10 data register high (adrh) see page 48. read:000000ad9ad8 write:rrrrrrrr reset:00000000 $003e adc10 data register low (adrl) see page 48. read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write:rrrrrrrr reset:00000000 $003f adc10 clock register (adclk) see page 49. read: adlpc adiv1 adiv0 adiclk mode1 mode0 adlsmp aclken write: reset:00000000 $fe00 break status register (bsr) see page 195. read: rrrrrr sbsw r write: 0 reset: 0 $fe01 sim reset status register (srsr) see page 152. read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe02 break auxiliary register (brkar) see page 195. read:0000000 bdcop write: reset:00000000 $fe03 break flag control register (bfcr) see page 195. read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) see page 149. read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) see page 149. read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) see page 149. read: if22 if21 if20 if19 if18 if17 if16 if15 write:rrrrrrrr reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 4 of 5)
direct page registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 29 $fe07 reserved $fe08 flash control register (flcr) see page 31. read: 0 0 0 0 hven mass erase pgm write: reset:00000000 $fe09 break address high register (brkh) see page 194. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $fe0a break address low register (brkl) see page 194. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 $fe0b break status and control register (brkscr) see page 194. read: brke brka 000000 write: reset:00000000 $fe0c lvi status register (lvisr) see page 91. read:lviout000000r write: reset:00000000 $fe0d $fe0f reserved $ffbe flash block protect register (flbpr) see page 36. read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset $ffbf reserved $ffc0 internal oscillator trim value read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset: resets to factory programmed value $ffc1 reserved $ffff cop control register (copctl) see page 63. read: low byte of reset vector write: writing clears cop counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 5 of 5)
memory mc68hc908qb8 data sheet, rev. 1 30 freescale semiconductor 2.5 random-access memory (ram) this mcu includes static ram. the locations in ram below $0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (bclr, bset, brclr, and brset). locating the most frequ ently accessed program variables in this area of ram is preferred. the ram retains data when the mcu is in low-power wait or stop mode. at power-on, the contents of ram are uninitialized. ram data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for ram retention. for compatibility with older m68hc 05 mcus, the hc08 resets the stack pointer to $00ff. in the devices that have ram above $00ff, it is usually best to reinit ialize the stack pointer to the top of the ram so the direct page ram can be used for frequently access ed ram variables and bit-addressable program variables. include the following 2-instruction sequence in your reset initialization routine (where ramlast is equated to the highest address of the ram). ldhx #ramlast+1 ;point one past ram txs ;sp<-(h:x-1) table 2-1. vector addresses vector priority ve ctor address vector lowest highest if22? if16 $ffd0? $ffdc not used if15 $ffde,f adc conversion complete vector if14 $ffe0,1 keyboard vector if13 $ffe2,3 spi transmit vector if12 $ffe4,5 spi receive vector if11 $ffe6,7 esci transmit vector if10 $ffe8,9 esci receive vector if9 $ffea,b esci error vector if8 ? not used if7 $ffee,f tim1 channel 3 vector if6 $fff0,1 tim1 channel 2 vector if5 $fff2,3 tim1 overflow vector if4 $fff4,5 tim1 channel 1 vector if3 $fff6,7 tim1 channel 0 vector if2 ? not used if1 $fffa,b irq vector ? $fffc,d swi vector ? $fffe,f reset vector
flash memory (flash) mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 31 2.6 flash memory (flash) the flash memory is intended primarily for program storage. in-circuit programming allows the operating program to be loaded into the flash memory after final assembly of the application product. it is possible to program the entire array through the single-wire monitor mode interface. because no special voltages are needed for flash erase and programming operations, in -application programming is also possible through other software-controlled communication paths. this subsection describes the operation of t he embedded flash memory. the flash memory can be read, programmed, and erased from the internal v dd supply. the program and erase operations are enabled through the use of an internal charge pump. the minimum size of flash memory that can be erased is 64 bytes; and the maximum size of flash memory that can be programmed in a program cycle is 32 bytes (a row). program and erase operations are facilitated through control bits in the flash cont rol register (flcr). details for these operations appear later in this section. note an erased bit reads as a 1 and a programmed bit reads as a 0. a security feature prevents viewing of the flash contents. (1) 2.6.1 flash control register the flash control register (flcr) controls flash program and erase operations. hven ? high voltage enable bit this read/write bit enables high voltage from the c harge pump to the memory for either program or erase operation. it can only be set if either pgm =1 or erase =1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit this read/write bit configures the memory for mass erase operation. 1 = mass erase operation selected 0 = mass erase operation unselected 1. no security feature is abso lutely secure. however, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users. bit 7654321bit 0 read:0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 2-3. flash control register (flcr)
memory mc68hc908qb8 data sheet, rev. 1 32 freescale semiconductor erase ? erase control bit this read/write bit configures t he memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit configures the memory for progr am operation. pgm is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected 2.6.2 flash page erase operation use the following procedure to erase a page of flas h memory. a page consists of 64 consecutive bytes starting from addresses $xx00, $xx40, $xx80, or $xxc0. the 48-byte user interrupt vectors area also forms a page. any flash memory page can be erased alone. 1. set the erase bit and clear the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash location within the address range of the block to be erased. 4. wait for a time, t nvs . 5. set the hven bit. 6. wait for a time, t erase . 7. clear the erase bit. 8. wait for a time, t nvh . 9. clear the hven bit. 10. after time, t rcv , the memory can be accessed in read mode again. note the cop register at location $ffff should not be written between steps 5-9, when the hven bit is set. since this register is located at a valid flash address, unpredictable behavior may occur if this location is written while hven is set. note programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, other unrelated operations may occur between the steps. caution a page erase of the vector page will er ase the internal oscillator trim value at $ffc0.
flash memory (flash) mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 33 2.6.3 flash m ass erase operation use the following procedure to erase the entire flash memory to read as a 1: 1. set both the erase bit and the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash address (1) within the flash memory address range. 4. wait for a time, t nvs . 5. set the hven bit. 6. wait for a time, t merase . 7. clear the erase and mass bits. note mass erase is disabled whenever any block is protected (flbpr does not equal $ff). 8. wait for a time, t nvhl . 9. clear the hven bit. 10. after time, t rcv , the memory can be accessed in read mode again. note programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, other unrelated operations may occur between the steps. caution a mass erase will erase the intern al oscillator trim value at $ffc0. 2.6.4 flash program operation programming of the flash memory is done on a row basis. a row consists of 32 consecutive bytes starting from addresses $xx00, $xx20, $xx40, $ xx60, $xx80, $xxa0, $xxc0, or $xxe0. use the following step-by-step procedure to program a row of flash memory figure 2-4 shows a flowchart of the programming algorithm. note do not program any byte in the flash more than once after a successful erase operation. reprogramming bits to a byte which is already programmed is not allowed without first erasing the page in which the byte resides or mass erasing the entire flash memory. programming without first erasing may disturb data stored in the flash. 1. set the pgm bit. this configures the memory for program operation and enables the latching of address and data for programming. 2. read the flash block protect register. 3. write any data to any flash location within the address range desired. 4. wait for a time, t nvs . 5. set the hven bit. 1. when in monitor mode, with security sequence failed (see 17.3.2 security ), write to the flash block protect register in- stead of any flash address.
memory mc68hc908qb8 data sheet, rev. 1 34 freescale semiconductor 6. wait for a time, t pgs . 7. write data to the flash address being programmed (1) . 8. wait for time, t prog . 9. repeat step 7 and 8 until all desir ed bytes within the row are programmed. 10. clear the pgm bit (1) . 11. wait for time, t nvh . 12. clear the hven bit. 13. after time, t rcv , the memory can be accessed in read mode again. note the cop register at location $ffff should not be written between steps 5-12, when the hven bit is set. since this register is located at a valid flash address, unpredictable behavior may occur if this location is written while hven is set. this program sequence is repeated throughout the memory until all data is programmed. note programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. do not exceed t prog maximum, see 18.17 memory characteristics . 2.6.5 flash protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. this protection is done by use of a flash block protect register (flbpr). the flbpr determines the range of the flash memory which is to be protected. the range of the protected area starts from a location defined by flbpr and ends to the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or program operations. note in performing a program or erase operation, the flash block protect register must be read after setting the pgm or erase bit and before asserting the hven bit. when the flbpr is programmed with all 0 s, the enti re memory is protected from being programmed and erased. when all the bits are erased (all 1?s), the entire memory is accessible for program and erase. when bits within the flbpr are programmed, they lock a block of memory. the address ranges are shown in 2.6.6 flash block protect register . once the flbpr is programmed with a value other than $ff, any erase or program of the flbpr or the pr otected block of flash memory is prohibited. mass erase is disabled whenever any bloc k is protected (flbpr does not equal $ff). the flbpr itself can be erased or programmed only with an external voltage, v tst , present on the irq pin. this voltage also allows entry from reset into the monitor mode. 1. the time between each flash address change, or the time between the last flash address programmed to clearing pgm bit, must not exceed the maximum programming time, t prog maximum.
flash memory (flash) mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 35 figure 2-4. flash programming flowchart set hven bit write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 7 to step 7 loop), must not exceed the maximum programming time, t prog max. or the time between the last flash address programmed to clearing pgm bit (step 7 to step 10) notes: 1 3 4 5 6 7 8 10 11 12 13 algorithm for programming a row (32 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased. 9 read the flash block protect register 2
memory mc68hc908qb8 data sheet, rev. 1 36 freescale semiconductor 2.6.6 flash bloc k protect register the flash block protect register is implemented as a byte within the flash memory, and therefore can only be written during a programming sequence of the flash memory. the value in this register determines the starting address of the protected range within the flash memory. bpr[7:0] ? flash protection register bits [7:0] these eight bits in flbpr represent bits [13:6] of a 16-bit memory address. bits [15:14] are 1s and bits [5:0] are 0s. the resultant 16-bit address is used for specifying the start address of the flash memory for block protection. the flash is protected from this star t address to the end of flash memory, at $ffff. with this mechanism, the protect start address can be xx00, xx40, xx80, or xxc0 within the flash memory. see figure 2-6 and table 2-2 . figure 2-6. flash block protect start address bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset. initial value from factory is 1. write to this register is by a programming sequence to the flash memory. figure 2-5. flash block protect register (flbpr) table 2-2. examples of protect start address bpr[7:0] start of address of protect range $00?$77 the entire flash memory is protected. $78 ( 0111 1000 )$de00 (11 01 1110 00 00 0000) $79 ( 0111 1001 )$de40 (11 01 1110 01 00 0000) $7a ( 0111 1010 )$de80 (11 01 1110 10 00 0000) $7b ( 0111 1011 )$dfc0 (11 01 1110 11 00 0000) and so on... $de ( 1101 1110 )$f780 (11 11 0111 10 00 0000) $df ( 1101 1111 )$f7c0 (11 11 0111 11 00 0000) $fe ( 1111 1110 ) $ff80 (11 11 1111 10 00 0000) flbpr, osctrim, and vectors are protected $ff the entire flash memory is not protected. 0 0 0 0 0 1 1 flbpr value start address of 16-bit memory address flash block protect 0
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 37 chapter 3 analog-to-digital converter (adc10) module 3.1 introduction this section describes the 10-bit successive a pproximation analog-to-digital converter (adc10). the adc10 module shares its pins with general-purpose input/output (i/o) port pins. see figure 3-1 for port location of these shared pins. the adc10 on this mcu uses v dd and v ss as its supply and reference pins. this mcu uses busclkx4 as its alternate cl ock source for the adc. this mcu does not have a hardware conversion trigger. 3.2 features features of the adc10 module include: linear successive approximation algorithm with 10-bit resolution output formatted in 10- or 8-bit right-justified format single or continuous conversion (autom atic power-down in single conversion mode) configurable sample time and conversion speed (to save power) conversion complete flag and interrupt input clock selectable from up to three sources operation in wait and stop modes for lower noise operation selectable asynchronous hardware conversion trigger 3.3 functional description the adc10 uses successive approximation to convert the input sample taken from advin to a digital representation. the approximation is taken and then r ounded to the nearest 10- or 8-bit value to provide greater accuracy and to provide a more robust mechani sm for achieving the ideal code-transition voltage. figure 3-2 shows a block diagram of the adc10 for proper conversion, the voltage on advin must fall between v refh and v refl . if advin is equal to or exceeds v refh , the converter circuit converts the signal to $3ff for a 10-bit representation or $ff for a 8-bit representation. if advin is equal to or less than v refl , the converter circuit converts it to $000. input voltages between v refh and v refl are straight-line linear conversions. note input voltage must not exceed the analog supply voltages.
analog-to-digital conv erter (adc10) module mc68hc908qb8 data sheet, rev. 1 38 freescale semiconductor figure 3-1. block diagram highlighting adc10 block and pins rst , irq : pins have internal pull up device all port pins have prog rammable pull up device pta[0:5]: higher current sink and source capability pta0/tch0/ad0/kbi0 pta1/tch1/ad1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 4-channel 16-bit timer module keyboard interrupt module external interrupt module auto wakeup low-voltage inhibit cop module 10-channel 10-bit adc enhanced serial ptb0/sck/ad4 ptb ddrb m68hc08 cpu pta ddra ptb1/mosi/ad5 ptb2/miso/ad6 ptb3/ss /ad7 ptb4/rxd/ad8 ptb5/txd/ad9 ptb6/tch2 ptb7/tch3 power supply v dd v ss clock generator communications interface module module serial peripheral interface mc68hc908qb8 8192 bytes user flash 256 bytes user ram mc68hc908qb8 monitor rom break module development support
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 39 figure 3-2. adc10 block diagram the adc10 can perform an analog-to-digital conversion on one of the software selectable channels. the output of the input multiplexer (advin) is converted by a successive approximation algorithm into a 10-bit digital result. when the conversion is completed, the result is placed in the data registers (adrh and adrl). in 8-bit mode, the result is rounded to 8 bits and placed in adrl. the conversion complete flag is then set and an interrupt is generated if the interrupt has been enabled. 3.3.1 clock select and divide circuit the clock select and divide circuit selects one of three clock sources and divides it by a configurable value to generate the input clock to the converter (adck). the clock can be selected from one of the following sources: the asynchronous clock source (aclk) ? this cl ock source is generated from a dedicated clock source which is enabled when the adc10 is converti ng and the clock source is selected by setting the aclken bit. when the adlpc bit is clear, this clock operates from 1?2 mhz; when adlpc is set it operates at 0.5?1 mhz. this clock is not disabled in stop and allows conversions in stop mode for lower noise operation. alternate clock source ? this clock source is equal to the external oscillator clock or a four times the bus clock. the alternate clock source is mcu specific, see 3.1 introduction to determine source and availability of this clock source option. th is clock is selected when adiclk and aclken are both low. the bus clock ? this clock source is equal to the bus frequency. this clock is selected when adiclk is high and aclken is low. ad0 ? adn v refh v refl advin adch control sequencer initialize sample convert transfer abort adck bus clock alternate clock source adiclk adiv aclk adco adcsc adlsmp adlpc mode complete data registers adrh:adrl sar converter aien coco interrupt aien coco 1 2 1 2 mcu stop adhwt adclk aclken async clock generator clock divide
analog-to-digital conv erter (adc10) module mc68hc908qb8 data sheet, rev. 1 40 freescale semiconductor whichever clock is selected, its frequency must fall within the acceptable frequency range for adck. if the available clocks are too slow, the adc10 will not perform according to specif ications. if the available clocks are too fast, then the clock must be divided to the appropriate frequency. this divider is specified by the adiv[1:0] bits and can be divide-by 1, 2, 4, or 8. 3.3.2 input select and pin control only one analog input may be used for conversion at any given time. the channel select bits in adcsc are used to select the input signal for conversion. 3.3.3 conversion control conversions can be performed in either 10-bit mode or 8-bit mode as determined by the mode bits. conversions can be initiated by either a software or hardware trigger. in addition, the adc10 module can be configured for low power operation, long sample time, and continuous conversion. 3.3.3.1 initiating conversions a conversion is initiated: following a write to adcsc (with adch bits not al l 1s) if software triggered operation is selected. following a hardware trigger event if hardware triggered operation is selected. following the transfer of the result to the da ta registers when conti nuous conversion is enabled. if continuous conversions are enabled a new conversion is automatically initiated after the completion of the current conversion. in software triggered operati on, continuous conversions begin after adcsc is written and continue until aborted. in hardware tri ggered operation, continuous conversions begin after a hardware trigger event and continue until aborted. 3.3.3.2 completing conversions a conversion is completed when the result of the conversion is transferred into the data result registers, adrh and adrl. this is indicated by the setting of the coco bit. an interrupt is generated if aien is high at the time that coco is set. a blocking mechanism prevents a new result from ov erwriting previous data in adrh and adrl if the previous data is in the proces s of being read while in 10-bit mode (adrh has been read but adrl has not). in this case the data transfer is blocked, coco is not set, and the new result is lost. when a data transfer is blocked, another conversion is initiated r egardless of the state of adco (single or continuous conversions enabled). if single conversions are enab led, this could result in several discarded conversions and excess power consumption. to avoid th is issue, the data registers must not be read after initiating a single conversion until the conversion completes. 3.3.3.3 aborting conversions any conversion in progress will be aborted when: a write to adcsc occurs (the current conversi on will be aborted and a new conversion will be initiated, if adch are not all 1s). a write to adclk occurs. the mcu is reset. the mcu enters stop mode with aclk not enabled.
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 41 when a conversion is aborted, the contents of the dat a registers, adrh and adrl, are not altered but continue to be the values transferred after the completi on of the last successful conversion. in the case that the conversion was aborted by a reset, adrh and adrl return to their reset states. upon reset or when a conversion is otherwise aborte d, the adc10 module will enter a low power, inactive state. in this state, all internal clocks and refere nces are disabled. this state is entered asynchronously and immediately upon abo rting of a conversion. 3.3.3.4 total conversion time the total conversion time depends on many factors such as sample time, bus frequency, whether aclken is set, and synchronization time. the total conversion time is summarized in table 3-1 . the maximum total conversion time for a single conversion or the first conversion in continuous conversion mode is determined by the clock source chosen and the divide ratio selected. the clock source is selectable by the adiclk and aclken bits, and the divide ratio is specified by the adiv bits. for example, if the alternate clock source is 16 mhz and is selected as the input clock source, the input clock divide-by-8 ratio is selected and the bus freque ncy is 4 mhz, then the conversion time for a single 10-bit conversion is: note the adck frequency must be between f adck minimum and f adck maximum to meet a/d specifications. table 3-1. total conversion time versus control conditions conversion mode aclken m aximum conversion time 8-bit mode (short sample ? adlsmp = 0): single or 1st continuous single or 1st continuous subsequent continuous (f bus f adck ) 0 1 x 18 adck + 3 bus clock 18 adck + 3 bus clock + 5 s 16 adck 8-bit mode (long sample ? adlsmp = 1): single or 1st continuous single or 1st continuous subsequent continuous (f bus f adck ) 0 1 x 38 adck + 3 bus clock 38 adck + 3 bus clock + 5 s 36 adck 10-bit mode (short sample ? adlsmp = 0): single or 1st continuous single or 1st continuous subsequent continuous (f bus f adck ) 0 1 x 21 adck + 3 bus clock 21 adck + 3 bus clock + 5 s 19 adck 10-bit mode (long sample ? adlsmp = 1): single or 1st continuous single or 1st continuous subsequent continuous (f bus f adck ) 0 1 x 41 adck + 3 bus clock 41 adck + 3 bus clock + 5 s 39 adck 21 adck cycles maximum conversion time = 16 mhz/8 number of bus cycles = 11.25 s x 4 mhz = 45 cycles 3 bus cycles 4 mhz + = 11.25 s
analog-to-digital conv erter (adc10) module mc68hc908qb8 data sheet, rev. 1 42 freescale semiconductor 3.3.4 sources of error several sources of error exist for adc conversion s. these are discussed in the following sections. 3.3.4.1 sampling error for proper conversions, the input must be sampled long enough to achieve the proper accuracy. given the maximum input resistance of approximately 15 k ? and input capacitance of approximately 10 pf, sampling to within 1/4 lsb (at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles / 2 mhz maximum adck frequency) provided the resistance of the external analog source (r as ) is kept below 10 k ? . higher source resistances or higher-a ccuracy sampling is possible by setting adlsmp (to increase the sample window to 23.5 cycles) or decreasing adck frequency to increase sample time. 3.3.4.2 pin leakage error leakage on the i/o pins can cause conversion error if the external analog source resistance (r as ) is high. if this error cannot be tolerated by the application, keep r as lower than v advin / (4096*i leak ) for less than 1/4 lsb leakage error (at 10-bit resolution). 3.3.4.3 noise-induced errors system noise which occurs during the sample or c onversion process can affect the accuracy of the conversion. the adc10 accuracy numbers are guarante ed as specified only if the following conditions are met: there is a 0.1 f low-esr capacitor from v refh to v refl (if available). there is a 0.1 f low-esr capacitor from v dda to v ssa (if available). if inductive isolation is used from the primary supply, an additional 1 f capacitor is placed from v dda to v ssa (if available). v ssa and v refl (if available) is connected to v ss at a quiet point in the ground plane. the mcu is placed in wait mode immediately afte r initiating the conversion (next instruction after write to adcsc). there is no i/o switching, input or output, on the mcu during the conversion. there are some situations where external system acti vity causes radiated or conducted noise emissions or excessive v dd noise is coupled into the adc10. in these cases, or when the mcu cannot be placed in wait or i/o activity cannot be halted, the foll owing recommendations may reduce the effect of noise on the accuracy: place a 0.01 f capacitor on the selected input channel to v refl or v ssa (if available). this will improve noise issues but will affect sample ra te based on the external analog source resistance. operate the adc10 in stop mode by setting aclken, selecting the channel in adcsc, and executing a stop instruction. this will reduce v dd noise but will increase effective conversion time due to stop recovery. average the input by converting the output many times in succession and dividing the sum of the results. four samples are required to eliminate the effect of a 1 lsb , one-time error. reduce the effect of synchronous noise by opera ting off the asynchronous clock (aclken=1) and averaging. noise that is synchronous to the adck cannot be averaged out.
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 43 3.3.4.4 code width and quantization error the adc10 quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). each step ideally has the same height (1 code) and width. t he width is defined as the delta between the transition points from one code to the next. the ideal code width for an n bit converter (in this case n can be 8 or 10), defined as 1 lsb , is: 1 lsb = (v refh ?v refl ) / 2 n because of this quantization, there is an inherent quan tization error. because the converter performs a conversion and then rounds to 8 or 10 bits, the code wi ll transition when the voltage is at the midpoint between the points where the straight line transfer f unction is exactly represented by the actual transfer function. therefore, the quantization error will be 1/2 lsb in 8- or 10-bit mode. as a consequence, however, the code width of the fi rst ($000) conversion is only 1/2 lsb and the code width of the last ($ff or $3ff) is 1.5 lsb . 3.3.4.5 linearity errors the adc10 may also exhibit non-linearity of several forms. every effort has been made to reduce these errors but the user should be aware of them becaus e they affect overall accuracy. these errors are: zero-scale error (e zs ) (sometimes called offset) ? this e rror is defined as the difference between the actual code width of the first c onversion and the ideal code width (1/2 lsb ). note, if the first conversion is $001, then the difference between the actual $001 code width and its ideal (1 lsb ) is used. full-scale error (e fs ) ? this error is defined as the differ ence between the actual code width of the last conversion and the ideal code width (1.5 lsb ). note, if the last conversion is $3fe, then the difference between the actual $3fe code width and its ideal (1 lsb ) is used. differential non-linearity (dnl) ? this error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. integral non-linearity (inl) ? this error is define d as the highest-value the (absolute value of the) running sum of dnl achieves. more simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. total unadjusted error (tue) ? this error is defi ned as the difference between the actual transfer function and the ideal straight-l ine transfer function, and therefore includes all forms of error. 3.3.4.6 code jitter, non-monotonicity and missing codes analog-to-digital converters are susceptible to thr ee special forms of error. these are code jitter, non-monotonicity, and missing codes. code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. ideally, when the input voltage is infinitesimally smaller than the transition voltage, the converter yields the lower code (and vice-versa). however, even very small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. this range is normally around 1/2 lsb but will increase with noise. non-monotonicity is defined as when, except for c ode jitter, the converter converts to a lower code for a higher input voltage. missing codes are those which are never converted for any input value. in 8-bit or 10-bit mode, the adc10 is guaranteed to be monot onic and to have no missing codes.
analog-to-digital conv erter (adc10) module mc68hc908qb8 data sheet, rev. 1 44 freescale semiconductor 3.4 interrupts when aien is set, the adc10 is capable of generat ing a cpu interrupt after each conversion. a cpu interrupt is generated when the conversion completes (indicated by coco being set). coco will set at the end of a conversion regardless of the state of aien. 3.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 3.5.1 wait mode the adc10 will continue the conversion process and will generate an interrupt following a conversion if aien is set. if the adc10 is not required to bring the mcu out of wait mode, ensure that the adc10 is not in continuous conversion mode by clearing adco in the adc10 st atus and control register before executing the wait instruction. in single conver sion mode the adc10 automatically enters a low-power state when the conversion is complete. it is not necessary to set the channel select bits (adch[4:0]) to all 1s to enter a low power state. 3.5.2 stop mode if aclken is clear, executing a stop instruction will abort the current conversion and place the adc10 in a low-power state. upon return from stop mode, a write to adcsc is requir ed to resume conversions, and the result stored in adrh and adrl will represent the last completed conversion until the new conversion completes. if aclken is set, the adc10 continues normal operation during stop mode. the adc10 will continue the conversion process and will generate an interrupt followin g a conversion if aien is set. if the adc10 is not required to bring the mcu out of stop mode, ensur e that the adc10 is not in continuous conversion mode by clearing adco in the adc10 status and contro l register before executing the stop instruction. in single conversion mode the adc1 0 automatically enters a low-power state when the conversion is complete. it is not necessary to set the channel select bi ts (adch[4:0]) to all 1s to enter a low-power state. if aclken is set, a conversion can be initiated wh ile in stop using the external hardware trigger adextco when in external convert mode. the adc10 will operate in a low-power mode until the trigger is asserted, at which point it will perform a conversi on and assert the interrupt when complete (if aien is set). 3.6 adc10 during break interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. bcfe in the break flag control register (bfcr) enables software to clear status bits during the break state. see bfcr in the sim section of this data sheet . to allow software to clear status bits during a break interrupt, write a 1 to bcfe. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to bcfe. with bcfe cleared (its default state), software can read and write registers during the break stat e without affecting status bits. some status bits have a two-step read/write clearing procedure. if softw are does the first step on such a bit before the
i/o signals mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 45 break, the bit cannot change during the break state as long as bcfe is cleared. after the break, doing the second step clears the status bit. 3.7 i/o signals the adc10 module shares its pins with general-purpose input/output (i/o) port pins. see figure 3-1 for port location of these shared pins. the adc10 on this mcu uses v dd and v ss as its supply and reference pins. this mcu does not have an external trigger source. 3.7.1 adc10 analog power pin (v dda ) the adc10 analog portion uses v dda as its power pin. in some packages, v dda is connected internally to v dd . if externally available, connect the v dda pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v dda for good results. note if externally available, route v dda carefully for maximum noise immunity and place bypass capacitors as near as possible to the package. 3.7.2 adc10 analog ground pin (v ssa ) the adc10 analog portion uses v ssa as its ground pin. in some packages, v ssa is connected internally to v ss . if externally available, connect the v ssa pin to the same voltage potential as v ss . in cases where separate power supplies are used for analog and digital power, the ground connection between these supplies should be at the v ssa pin. this should be the only ground connection between these supplies if possible. the v ssa pin makes a good single point ground location. 3.7.3 adc10 voltage reference high pin (v refh ) v refh is the power supply for setting the high-referenc e voltage for the converter. in some packages, v refh is connected internally to v dda . if externally available, v refh may be connected to the same potential as v dda , or may be driven by an external source that is between the minimum v dda spec and the v dda potential (v refh must never exceed v dda ). note route v refh carefully for maximum nois e immunity and place bypass capacitors as near as possible to the package. ac current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the v refh and v refl loop. the best external component to meet this current demand is a 0.1 f capacitor with good high frequency characteristics. this capacitor is connected between v refh and v refl and must be placed as close as possible to the package pins. resistance in the path is not recommended because t he current will cause a voltage drop which could result in conversion errors. inductance in this path must be minimum (parasitic only). 3.7.4 adc10 voltage reference low pin (v refl ) v refl is the power supply for setting the low-reference voltage for the converter. in some packages, v refl is connected internally to v ssa . if externally available, connect the v refl pin to the same voltage potential as v ssa . there will be a brief current associated with v refl when the sampling capacitor is
analog-to-digital conv erter (adc10) module mc68hc908qb8 data sheet, rev. 1 46 freescale semiconductor charging. if externally available, connect the v refl pin to the same potential as v ssa at the single point ground location. 3.7.5 adc10 channel pins (adn) the adc10 has multiple input channels. empirica l data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. 0.01 f capacitors with good high-frequency characteristics are sufficien t. these capacitors are not necessary in all cases, but when used they must be placed as close as possible to the package pins and be referenced to v ssa . 3.8 registers these registers control and monitor operation of the adc10: adc10 status and control register, adcsc adc10 data registers, adrh and adrl adc10 clock register, adclk 3.8.1 adc10 status and control register this section describes the function of the adc10 status and control register (adcsc). writing adcsc aborts the current c onversion and initiates a new conversion (if the adch[4:0] bits are equal to a value other than all 1s). coco ? conversion complete bit coco is a read-only bit which is set each time a conv ersion is completed. this bit is cleared whenever the status and control register is written or whenever the data register (low) is read. 1 = conversion completed 0 = conversion not completed aien ? adc10 interrupt enable bit when this bit is set, an interrupt is generated at the end of a conversion. the interrupt signal is cleared when the data register is read or t he status/control register is written. 1 = adc10 interrupt enabled 0 = adc10 interrupt disabled adco ? adc10 continuous conversion bit when this bit is set, the adc10 will begin to convert samples continuously (continuous conversion mode) and update the result registers at the end of each conversion, provided the adch[4:0] bits do not decode to all 1s. the adc10 will continue to convert until the mcu enters reset, the mcu enters stop mode (if aclken is clear), adclk is written, or until adcsc is written again. if stop is entered bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 = unimplemented figure 3-3. adc10 status and control register (adcsc)
registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 47 (with aclken low), continuous conversions will cease and can be restarted only with a write to adcsc. any write to adcsc with adco set and th e adch bits not all 1s will abort the current conversion and begin co ntinuous conversions. if the bus frequency is less than the adck frequency, precise sample time for continuous conversions cannot be guaranteed in short-sample mode (adlsm p = 0). if the bus frequency is less than 1/11th of the adck frequency, precise sample time fo r continuous conversions cannot be guaranteed in long-sample mode (adlsmp = 1). when clear, the adc10 will perform a single co nversion (single conversi on mode) each time adcsc is written (assuming the adch[4:0] bits do not decode all 1s). 1 = continuous conversion following a write to adcsc 0 = one conversion following a write to adcsc adch[4:0] ? channel select bits the adch[4:0] bits form a 5-bit field that is us ed to select one of the input channels. the input channels are detailed in table 3-2 . the successive approximation c onverter subsystem is turned off when the channel select bits are all set to 1. this feature allows explicit disabling of the adc10 and isolation of the input channel from the i/o pad. te rminating continuous conversion mode this way will prevent an additional, single conver sion from being performed. it is not necessary to set the channel select bits to all 1s to place the adc10 in a low-power state, however, because the module is automatically placed in a low-power state when a conversion completes. table 3-2. input channel select adch4 adch3 adch2 adch1 adch0 input select (1) 1. if any unused or reserved channels are selected, the re sulting conversion will be unknown. 00000 ad0 00001 ad1 00010 ad2 00011 ad3 00100 ad4 00101 ad5 00110 ad6 00111 ad7 01000 unused continuing through unused 10111 unused 11000 ad8 11001 ad9 11010 bandgap ref (2) 2. requires lvi to be powered (lvipwrd =0, in config1) 11011 reserved 11100 reserved 11101 v refh 11110 v refl 11111low-power state
analog-to-digital conv erter (adc10) module mc68hc908qb8 data sheet, rev. 1 48 freescale semiconductor 3.8.2 adc10 result hi gh register (adrh) this register holds the msbs of the result and is upd ated each time a conversion completes. all other bits read as 0s. reading adrh prevents the adc10 from tr ansferring subsequent conversion results into the result registers until adrl is read. if adrl is not read until the after next conversion is completed, then the intermediate conversion result will be lost. in 8-bit mode, this regi ster contains no interlocking with adrl. 3.8.3 adc10 result low register (adrl) this register holds the lsbs of the result. this register is updated each time a conversion completes. reading adrh prevents the adc10 fr om transferring subseq uent conversion results into the result registers until adrl is read. if adrl is not read until the after next conversion is completed, then the intermediate conversion result will be lost. in 8-bit mode, there is no interlocking with adrh. bit 7654321bit 0 read:00000000 write: reset:00000000 = unimplemented figure 3-4. adc10 data register high (adrh), 8-bit mode bit 7654321bit 0 read:000000ad9ad8 write: reset:00000000 = unimplemented figure 3-5. adc10 data register high (adrh), 10-bit mode bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset:00000000 = unimplemented figure 3-6. adc10 data register low (adrl)
registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 49 3.8.4 adc10 clock register (adclk) this register selects the clock frequency for the adc10 and the modes of operation. adlpc ? adc10 low-power configuration bit adlpc controls the speed and power configuration of the successive approximation converter. this is used to optimize power consumption when higher sample rates are not required. 1 = low-power configuration: the power is re duced at the expense of maximum clock speed. 0 = high-speed configuration adiv[1:0] ? adc10 clock divider bits adiv1 and adiv0 select the divide ratio used by the adc10 to generate the internal clock adck. table 3-3 shows the available clock configurations. adiclk ? input clock select bit if aclken is clear, adiclk selects either the bus cl ock or an alternate clock s ource as the input clock source to generate the internal clock adck. if the alternate clock source is less than the minimum clock speed, use the internally-generated bus clock as the clock source. as l ong as the internal clock adck, which is equal to the selected input cl ock divided by adiv, is at a frequency (f adck ) between the minimum and maximum clock speeds (consider ing alpc), correct operation can be guaranteed. 1 = the internal bus clock is se lected as the input clock source 0 = the alternate clock source is selected mode[1:0] ? 10- or 8-bit or hardware triggered mode selection these bits select 10- or 8-bit operation. the succ essive approximation converter generates a result that is rounded to 8- or 10-bit value based on the mode selection. this rounding process sets the transfer function to transition at the midpoint be tween the ideal code voltages, causing a quantization error of 1/2 lsb . reset returns 8-bit mode. 00 = 8-bit, right-justified, adcsc software triggered mode enabled 01 = 10-bit, right-justified, adcsc software triggered mode enabled 10 = reserved 11 = 10-bit, right-justified, hardware triggered mode enabled bit 7654321bit 0 read: adlpc adiv1 adiv0 adiclk mode1 mode0 adlsmp aclken write: reset:00000000 figure 3-7. adc10 clock register (adclk) table 3-3. adc10 clock divide ratio adiv1 adiv0 divide rati o (adiv) clock rate 0 0 1 input clock 1 0 1 2 input clock 2 1 0 4 input clock 4 1 1 8 input clock 8
analog-to-digital conv erter (adc10) module mc68hc908qb8 data sheet, rev. 1 50 freescale semiconductor adlsmp ? long sample time configuration this bit configures the sample time of the adc10 to either 3.5 or 23.5 adck clock cycles. this adjusts the sample period to allow higher impedance input s to be accurately sampled or to maximize conversion speed for lower impedance inputs. longer sample times can also be used to lower overall power consumption in continuous conversion m ode if high conversion rates are not required. 1 = long sample time (23.5 cycles) 0 = short sample time (3.5 cycles) aclken ? asynchronous clock source enable this bit enables the asynchronous cl ock source as the input clock to generate the internal clock adck, and allows operation in stop mode. the asynchron ous clock source will operate between 1 mhz and 2 mhz if adlpc is clear, and between 0.5 mhz and 1 mhz if adlpc is set. 1 = the asynchronous clock is selected as the input clock source (the clock generator is only enabled during the conversion) 0 = adiclk specifies the input clock source a nd conversions will not continue in stop mode
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 51 chapter 4 auto wakeup module (awu) 4.1 introduction this section describes the auto wakeup module (awu ). the awu generates a periodic interrupt during stop mode to wake the part up without requiring an external signal. figure 4-1 is a block diagram of the awu. figure 4-1. auto wakeup interrupt request generation logic 4.2 features features of the auto wakeup module include: one internal interrupt with separate interrupt enable bit, sharing the same keyboard interrupt vector and keyboard interrupt mask bit exit from low-power stop mode without external signals selectable timeout periods dedicated low-power internal oscillator s eparate from the main system clock sources option to allow bus clock source to run the awu if enabled in stop d r v dd int rc osc en 32 khz clk rst overflow autowugen short coprs (from config1) 1 = div 2 9 0 = div 2 14 e reset ackk clear rst reset clk (cgmxclk) busclkx4 istop awuireq clrlogic reset awul to pta read, bit 6 q awuie to kbi interrupt logic (see figure 9-2 ) busclkx4 osceninstop (from config2) m u x
auto wakeup module (awu) mc68hc908qb8 data sheet, rev. 1 52 freescale semiconductor 4.3 functional description the function of the auto wakeup logic is to generat e periodic wakeup requests to bring the microcontroller unit (mcu) out of stop mode. the wakeup requests ar e treated as regular keyboard interrupt requests, with the difference that instead of a pin, the in terrupt signal is generated by an internal logic. writing the awuie bit in the keyboard interrupt e nable register enables or disables the auto wakeup interrupt input (see figure 4-1 ). a 1 applied to the awuireq input with auto wakeup interrupt request enabled, latches an auto wakeup interrupt request. auto wakeup latch, awul, can be read directly from the bit 6 position of port a data register (pta). this is a read-only bit which is occupying an empty bit posi tion on pta. no pta associated registers, such as pta6 data direction or pta6 pullup exist for this bit. there exists two clock sources for the awu. an in ternal rc oscillator (exclusive for the auto wakeup feature, awu oscillator) drives the wakeup reques t generator provided the osceninstop bit in the config2 register figure 4-1 is cleared. if the application employs a crystal, for example, by setting the osceninstop bit the busclkx4 will drive the wakeup request generator to allow a more accurate wakeup. entering stop mode will enable the auto wakeup generation logic. once the overflow count is reached in the generator counter, a wakeup request, awuireq, is latched and sent to the kbi logic. see figure 4-1 . wakeup interrupt requests will onl y be serviced if the associated interrupt enable bit, awuie, in kbier is set. the awu shares the keyboard interrupt vector. the overflow count can be selected from two options defined by the co prs bit in config1. this bit was ?borrowed? from the computer operat ing properly (cop) using the fact that the cop feature is idle (no mcu clock available) in stop mode. the auto wakeup rc oscillator is highly dependent on op erating voltage and temperature. this feature is not recommended for use as a time-keeping function. the wakeup request is latched to allow the interrupt so urce identification. the latched value, awul, can be read directly from the bit 6 position of pta data r egister. this is a read-only bit which is occupying an empty bit position on pta. no pta associated register s, such as pta6 data, pta6 direction, and pta6 pullup exist for this bit. the latch can be cleared by writing to the ackk bit in the kbscr register. reset also clears the latch. awuie bit in kbi interrupt enable register (see figure 4-1 ) has no effect on awul reading. the awu oscillator and counters are inactive in normal operating mode and become active only upon entering stop mode. 4.4 interrupts the awu can generate an interrupt requests:. awu latch (awul) ? the awul bit is set when the awu counter overflows. the auto wakeup interrupt mask bit, awuie, is used to enable or disable awu interrupt requests. the awu shares its interrupt with the kbi vector.
low-power modes mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 53 4.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 4.5.1 wait mode the awu module remains inactive in wait mode. 4.5.2 stop mode when the awu module is enabled (awuie = 1 in the keyboard interrupt enable register) it is activated automatically upon entering stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. the awu counters start from 0 each time stop mode is entered. 4.6 registers the awu shares registers with the keyboard interrupt (kbi) module, the port a i/o module and configuration register 2. the following i/o registers control and monitor operation of the awu: port a data register (pta) keyboard interrupt status and control register (kbscr) keyboard interrupt enable register (kbier) configuration register 1 (config1) configuration register 2 (config2) 4.6.1 port a i/o register the port a data register (pta) contains a data latch for the state of the awu interrupt request, in addition to the data latches for port a. awul ? auto wakeup latch this is a read-only bit which has the value of the auto wakeup interrupt request latch. the wakeup request signal is generated internally. there is no pta6 port or any of the associated bits such as pta6 data direction or pullup bits. 1 = auto wakeup interrupt request is pending 0 = auto wakeup interrupt request is not pending note pta5?pta0 bits are not used in conj uction with the auto wakeup feature. to see a description of these bits, see 12.2.1 port a data register . bit 7654321bit 0 read: 0 awul pta5 pta4 pta3 pta2 pta1 pta0 write: reset: 0 0 unaffected by reset = unimplemented figure 4-2. port a data register (pta)
auto wakeup module (awu) mc68hc908qb8 data sheet, rev. 1 54 freescale semiconductor 4.6.2 keyboard status and contro l register the keyboard status and control register (kbscr): flags keyboard/auto wakeup interrupt requests acknowledges keyboard/auto wakeup interrupt requests masks keyboard/auto wakeup interrupt requests bits 7?4 ? not used these read-only bits always read as 0s. keyf ? keyboard flag bit this read-only bit is set when a keyboard interrupt is pending on port a or auto wakeup. reset clears the keyf bit. 1 = keyboard/auto wakeup interrupt pending 0 = no keyboard/auto wakeup interrupt pending ackk ? keyboard acknowledge bit writing a 1 to this write-only bit clears the keyb oard/auto wakeup interrupt request on port a and auto wakeup logic. ackk always reads as 0. reset clears ackk. imaskk? keyboard interrupt mask bit writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port a or auto wakeup. reset clears the imaskk bit. 1 = keyboard/auto wakeup interrupt requests masked 0 = keyboard/auto wakeup interrupt requests not masked note modek is not used in conjuction with the auto wakeup feature. to see a description of this bit, see 9.8.1 keyboard status and control register (kbscr) . 4.6.3 keyboard inte rrupt enable register the keyboard interrupt enable register (kbier) enables or disables the auto wakeup to operate as a keyboard/auto wakeup interrupt input. bit 7654321bit 0 read:0000 keyf 0 imaskk modek write: ackk reset:00000000 = unimplemented figure 4-3. keyboard status and control register (kbscr) bit 7654321bit 0 read: 0 awuie kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 4-4. keyboard interrupt enable register (kbier)
registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 55 awuie ? auto wakeup interrupt enable bit this read/write bit enables the auto wakeup interrupt input to latch interrupt requests. reset clears awuie. 1 = auto wakeup enabled as interrupt input 0 = auto wakeup not enabled as interrupt input note kbie5?kbie0 bits are not used in conjuction with the auto wakeup feature. to see a description of these bits, see 9.8.2 keyboard interrupt enable register (kbier) . 4.6.4 configuration register 2 the configuration register 2 (config2), is used to allow the bus clock source to run in stop. in this case, the clock, busclkx4 will be used to drive the awu request generator. osceninstop ? oscillator enable in stop mode bit osceninstop, when set, will allow the bus cl ock source (busclkx4) to generate clocks for the awu in stop mode. see 11.8.1 oscillator status and control register for information on enabling the external clock sources. 1 = oscillator enabled to operate during stop mode 0 = oscillator disabled during stop mode note irqpud, irqen, escibdsrc, and rsten bits are not used in conjuction with the auto wakeup feature. to see a description of these bits, see chapter 5 configuration register (config) . 4.6.5 configuration register 1 the configuration register 1 (config1), is used to select the period for the awu. the timeout will be based on the coprs bit along with the clock source for the awu. bit 76543 2 1 bit 0 read: irqpud irqen rrresci- bdsrc osceninstop rsten write: reset:00000 0 0 0 figure 4-5. configuration register 2 (config2) bit 7654321bit 0 read: coprs lvistop lvirstd lvipwrd lvitrip ssrec stop copd write: reset: por: 0 0 0 0 0 0 0 0 u 0 0 0 0 0 0 0 u = unaffected figure 4-6. configuration register 1 (config1)
auto wakeup module (awu) mc68hc908qb8 data sheet, rev. 1 56 freescale semiconductor coprs (in stop mode) ? auto wakeup period selection bit, depends on oscstopen in config2 and bus clock source (busclkx4). 1 = auto wakeup short cycle = 512 (intrcosc or busclkx4) 0 = auto wakeup long cycle = 16,384 (intrcosc or busclkx4) note lvistop, lvirst, lvipwrd, lvitrip, ssrec and copd bits are not used in conjuction with the auto wak eup feature. to see a description of these bits, see chapter 5 configuration register (config)
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 57 chapter 5 configuration register (config) 5.1 introduction this section describes the configuration registers (config1 and config2). the configuration registers enable or disable the following options: ? stop mode recovery time (32 busclkx4 cycles or 4096 busclkx4 cycles) stop instruction computer operating properly module (cop) cop reset period (coprs): 8176 busclkx4 or 262,128 busclkx4 low-voltage inhibit (lvi) enable and trip voltage selection auto wakeup timeout period allow clock source to remain enabled in stop enable irq pin disable irq pin pullup device enable rst pin clock source selection for the enhanced serial communication interface (esci) module 5.2 functional description the configuration registers are used in the initializatio n of various options. the c onfiguration registers can be written once after each reset. most of the configur ation register bits are cleared during reset. since the various options affect the operation of the microcontroller unit (mcu) it is recommended that this register be written immediately after reset. the configurati on registers are located at $001e and $001f, and may be read at anytime. note the config registers are one-time writable by the user after each reset. upon a reset, the config registers default to predetermined settings as shown in figure 5-1 and figure 5-2 . bit 7 6 5 4 3 2 1 bit 0 read: irqpud irqen r r r escibdsrc osceninstop rsten write: reset:000 0 0 0 0 u por:000 0 0 0 0 0 r = reserved u = unaffected figure 5-1. configuration register 2 (config2)
configuration register (config) mc68hc908qb8 data sheet, rev. 1 58 freescale semiconductor irqpud ? irq pin pullup control bit 1 = internal pullup is disconnected 0 = internal pullup is connected between irq pin and v dd irqen ? irq pin function selection bit 1 = interrupt request function active in pin 0 = interrupt request function inactive in pin escibdsrc ? esci baud rate clock source bit escibdsrc controls the clock source used for the esci. the setting of the bit affects the frequency at which the esci operates. 1 = internal data bus clock used as clock source for esci 0 = cgmxclk used as clock source for esci osceninstop? oscillator enable in stop mode bit osceninstop, when set, will allow the clock sour ce to continue to generate clocks in stop mode. this function can be used to keep the auto-wakeup running while the rest of the microcontroller stops. when clear, the clock source is disabled when the microcontroller enters stop mode. 1 = oscillator enabled to operate during stop mode 0 = oscillator disabled during stop mode rsten ? rst pin function selection 1 = reset function active in pin 0 = reset function inactive in pin note the rsten bit is cleared by a power-on reset (por) only. other resets will leave this bit unaffected. coprs (out of stop mode) ? cop reset period selection bit 1 = cop reset short cycle = 8176 busclkx4 0 = cop reset long cycle = 262,128 busclkx4 coprs (in stop mode) ? auto wakeup period selection bit, depends on oscstopen in config2 and external clock source 1 = auto wakeup short cycle = 512 (intrcosc or busclkx4) 0 = auto wakeup long cycle = 16,384 (intrcosc or busclkx4) lvistop ? lvi enable in stop mode bit when the lvipwrd bit is clear, setting the lvisto p bit enables the lvi to operate during stop mode. reset clears lvistop. 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode bit 7 6 5 4 3 2 1 bit 0 read: coprs lvistop lvirstd lvipwrd lvitrip ssrec stop copd write: reset:0000u000 por:00000000 u = unaffected figure 5-2. configuration register 1 (config1)
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 59 lvirstd ? lvi reset disable bit lvirstd disables the reset signal from the lvi module. 1 = lvi module resets disabled 0 = lvi module resets enabled lvipwrd ? lvi power disable bit lvipwrd disables the lvi module. 1 = lvi module power disabled 0 = lvi module power enabled lvitrip ? lvi trip point selection bit lvitrip selects the voltage operating mode of the lvi module. the voltage mode selected for the lvi should match the operating v dd for the lvi?s voltage trip points for each of the modes. 1 = lvi operates for a 5-v protection 0 = lvi operates for a 3-v protection note the lvitrip bit is cleared by a power-on reset (por) only. other resets will leave this bit unaffected. ssrec ? short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 busclkx4 cycles instead of a 4096 busclkx4 cycle delay. 1 = stop mode recovery after 32 busclkx4 cycles 0 = stop mode recovery after 4096 busclkx4 cycles note exiting stop mode by an lvi reset will result in the long stop recovery. when using the lvi during normal operation but disabling during stop mode, the lvi will have an enable time of t en . the system stabilization time for power-on reset and long stop recovery (both 4096 busclkx4 cycles) gives a delay longer than the lv i enable time for these startup scenarios. there is no period where the mcu is not protected from a low-power condition. however, when using the short stop recovery configuration option, the 32 bu sclkx4 delay must be greater than the lvi?s turn on time to avoid a period in startup where the lvi is not protecting the mcu. stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled
configuration register (config) mc68hc908qb8 data sheet, rev. 1 60 freescale semiconductor
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 61 chapter 6 computer operating properly (cop) 6.1 introduction the computer operating properly (cop) module cont ains a free-running counter that generates a reset if allowed to overflow. the cop modul e helps software recover from runaway code. prevent a cop reset by clearing the cop counter periodically. the cop m odule can be disabled through the copd bit in the configuration 1 (config1) register. 6.2 functional description figure 6-1. cop block diagram 1. see chapter 14 system integration module (sim) for more details. copctl write busclkx4 stop instruction sim reset circuit reset status register internal reset sources (1) sim module clear stages 5?12 12-bit sim counter clear all stages copd (from config1) reset copctl write clear cop module copen (from sim) cop clock cop timeout cop rate select (coprs from config1) 6-bit cop counter cop counter
computer operating properly (cop) mc68hc908qb8 data sheet, rev. 1 62 freescale semiconductor the cop counter is a free-running 6-bit counter prec eded by the 12-bit system integration module (sim) counter. if not cleared by software, the cop counter overflows and generates an asynchronous reset after 8176 or 262,128 busclkx4 cycles; depending on the state of the cop rate select bit, coprs, in configuration register 1. with a 262,128 busclkx4 cycle overflow option, the internal 12.8-mhz oscillator gives a cop tim eout period of 20.48 ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 12?5 of the sim counter. note service the cop immediately after rese t and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. a cop reset pulls the rst pin low (if the rsten bit is set in the config1 register) for 32 busclkx4 cycles and sets the cop bit in the reset status register (rsr). see 14.8.1 sim reset status register . note place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt s ubroutine could keep the cop from generating a reset even while the main program is not working properly. 6.3 i/o signals the following paragraphs describe the signals shown in figure 6-1 . 6.3.1 busclkx4 busclkx4 is the oscillator outpu t signal. busclkx4 frequency is eq ual to the internal oscillator frequency, the crystal frequency, or the rc-oscillator frequency. 6.3.2 stop instruction the stop instruction clears the sim counter. 6.3.3 copctl write writing any value to the cop control register (copctl) (see figure 6-2 ) clears the cop counter and clears stages 12?5 of the sim counter. reading the cop control register returns the low byte of the reset vector. 6.3.4 powe r-on reset the power-on reset (por) circuit in the sim clears the sim counter 4096 busclkx4 cycles after power up. 6.3.5 internal reset an internal reset clears the sim counter and the cop counter. 6.3.6 copd (cop disable) the copd signal reflects the state of the cop disable bit (copd) in the configur ation register (config). see chapter 5 configuration register (config) .
interrupts mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 63 6.3.7 coprs (cop rate select) the coprs signal reflects the state of the cop rate select bit (coprs) in the configuration register 1 (config1). see chapter 5 configuration register (config) . 6.4 interrupts the cop does not generate cpu interrupt requests. 6.5 monitor mode the cop is disabled in monitor mode when v tst is present on the irq pin. 6.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.6.1 wait mode the cop continues to operate during wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter. 6.6.2 stop mode stop mode turns off the busclkx4 input to the cop and clears the sim counter. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. 6.7 cop module during break mode the cop is disabled during a break interrupt with mo nitor mode when bdcop bit is set in break auxiliary register (brkar). 6.8 register the cop control register (copctl) is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and star ts a new timeout period. reading location $ffff returns the low byte of the reset vector. bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 6-2. cop control register (copctl)
computer operating properly (cop) mc68hc908qb8 data sheet, rev. 1 64 freescale semiconductor
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 65 chapter 7 central processor unit (cpu) 7.1 introduction the m68hc08 cpu (central processor unit) is an e nhanced and fully object-code- compatible version of the m68hc05 cpu. the cpu08 reference manual (document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 7.2 features features of the cpu include: object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-re gister manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes low-power stop and wait modes 7.3 cpu registers figure 7-1 shows the five cpu registers. cpu registers are not part of the memory map.
central processor unit (cpu) mc68hc908qb8 data sheet, rev. 1 66 freescale semiconductor figure 7-1. cpu registers 7.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. 7.3.2 index register the 16-bit index register allows i ndexed addressing of a 64-kbyte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, th e cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. bit 7654321bit 0 read: write: reset: unaffected by reset figure 7-2. accumulator (a) bit 151413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 7-3. index register (h:x) accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70
cpu registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 67 7.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset a ddressing modes, the stack pointer can function as an index register to access data on t he stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note the location of the stack is arbitrary and may be relocated anywhere in random-access memory (ram). moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 7.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increm ents to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. bit 151413121110987654321 bit 0 read: write: reset:0000000011111111 figure 7-4. stack pointer (sp) bit 151413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 7-5. program counter (pc)
central processor unit (cpu) mc68hc908qb8 data sheet, rev. 1 68 freescale semiconductor 7.3.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set per manently to 1. the following paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. th e daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cp u interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note to maintain m6805 family compatibil ity, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priori ty interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 7-6. condition code register (ccr)
arithmetic/logic unit (alu) mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 69 z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 7.4 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 7.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 7.5.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains cl ear. after exit by reset, the i bit is set. disables the cpu clock 7.5.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the conditi on code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. 7.6 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted.
central processor unit (cpu) mc68hc908qb8 data sheet, rev. 1 70 freescale semiconductor 7.7 instruction set summary table 7-1 provides a summary of the m68hc08 instruction set. table 7-1. instruction set summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ?? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 c b0 b7 0 b0 b7 c
instruction set summary mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 71 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 table 7-1. instruction set summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) mc68hc908qb8 data sheet, rev. 1 72 freescale semiconductor clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ?? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 table 7-1. instruction set summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
instruction set summary mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 73 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ??0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 table 7-1. instruction set summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0
central processor unit (cpu) mc68hc908qb8 data sheet, rev. 1 74 freescale semiconductor pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ?? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ?? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ? dir 35 dd 4 stop enable interrupts, stop processing, refer to mcu documentation i 0; stop processing ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 7-1. instruction set summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c
opcode map mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 75 7.8 opcode map see table 7-2 . swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 wait enable interrupts; wait for interrupt i bit 0; inhibit cpu clocking until interrupted ??0???inh 8f 1 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, pos t increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit ? not affected table 7-1. instruction set summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
mc68hc908qb8 data sheet, rev. 1 76 freescale semiconductor central processor unit (cpu) table 7-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1 2 3 4 5 6 9e6 7 8 9 a b c d 9ed e 9ee f 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4 sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3 sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4 sp2 3 add 2ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 77 chapter 8 external interrupt (irq) 8.1 introduction the irq (external interrupt) module provides a maskable interrupt input. irq functionality is enabled by setting configuration r egister 2 (config2) irqen bit accordingly. a zero disables the irq function and irq will assume the other shared functionalities. a one enables the irq function. see chapter 5 configuration register (config) for more information on enabling the irq pin. the irq pin shares its pin with general -purpose input/output (i/o) port pins. see figure 8-1 for port location of this shared pin. 8.2 features features of the irq module include: a dedicated external interrupt pin irq irq interrupt control bits programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge internal pullup device 8.3 functional description a low level applied to the external interrupt request (irq ) pin can latch a cpu interrupt request. figure 8-2 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. the irq latch remains set until one of the following actions occurs: irq vector fetch. an irq vector fetch automatical ly generates an interrupt acknowledge signal that clears the latch that caused the vector fetch. software clear. software can clear the irq latch by writing a 1 to the ack bit in the interrupt status and control register (intscr). reset. a reset automatical ly clears the irq latch. the external irq pin is falling edge sensitive out of reset and is software-configurable to be either falling edge or falling edge and low level sensitive. the mode bit in intscr controls the triggering sensitivity of the irq pin.
external interrupt (irq) mc68hc908qb8 data sheet, rev. 1 78 freescale semiconductor figure 8-1. block diagram highlighting irq block and pin when set, the imask bit in intscr masks the irq interrupt request. a latched interrupt request is not presented to the interrupt priori ty logic unless imask is clear. note the interrupt mask (i) in the condi tion code register (ccr) masks all interrupt requests, including the irq interrupt request. a falling edge on the irq pin can latch an interrupt request into the irq latch. an irq vector fetch, software clear, or reset clears the irq latch. rst , irq : pins have internal pull up device all port pins have prog rammable pull up device pta[0:5]: higher current sink and source capability pta0/tch0/ad0/kbi0 pta1/tch1/ad1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 4-channel 16-bit timer module keyboard interrupt module external interrupt module auto wakeup low-voltage inhibit cop module 10-channel 10-bit adc enhanced serial ptb0/sck/ad4 ptb ddrb m68hc08 cpu pta ddra ptb1/mosi/ad5 ptb2/miso/ad6 ptb3/ss /ad7 ptb4/rxd/ad8 ptb5/txd/ad9 ptb6/tch2 ptb7/tch3 power supply v dd v ss clock generator communications interface module module serial peripheral interface mc68hc908qb8 8192 bytes user flash 256 bytes user ram mc68hc908qb8 monitor rom break module development support
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 79 figure 8-2. irq module block diagram 8.3.1 mode = 1 if the mode bit is set, the irq pin is both falling edge sensitive and low level sensitive. with mode set, both of the following actions must occur to clear the irq interrupt request: return of the irq pin to a high level. as long as the irq pin is low, the irq request remains active. irq vector fetch or software clear. an irq vect or fetch generates an interrupt acknowledge signal to clear the irq latch. software generates the in terrupt acknowledge signal by writing a 1 to ack in intscr. the ack bit is useful in applications that poll the irq pin and require software to clear the irq latch. writing to ack prior to leaving an in terrupt service routine can also prevent spurious interrupts due to noise. setting ack does not affect subsequent transitions on the irq pin. a falling edge that occurs after writing to ack latches another interrupt request. if the irq mask bit, imask, is clear, the cpu loads the program co unter with the irq vector address. the irq vector fetch or software clear and the return of the irq pin to a high level may occur in any order. the interrupt request remains pending as long as the irq pin is low. a reset will clear the irq latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. use the bih or bil instruction to read the logic level on the irq pin. 8.3.2 mode = 0 if the mode bit is clear, the irq pin is falling edge sensitive only. with mode clear, an irq vector fetch or software clear immediately clears the irq latch. the irqf bit in intscr can be read to check for pending interrupts. the irqf bit is not affected by imask, which makes it useful in app lications where polling is preferred. note when using the level-sensitive interrupt trigger, avoid false irq interrupts by masking interrupt requests in the interrupt routine. imask dq ck clr irq high interrupt to mode select logic request v dd mode voltage detect irqf to cpu for bil/bih instructions internal address bus reset v dd internal pullup device ack irq synchronizer irq vector fetch decoder irq latch
external interrupt (irq) mc68hc908qb8 data sheet, rev. 1 80 freescale semiconductor 8.4 interrupts the following irq source can generate interrupt requests: interrupt flag (irqf) ? the irqf bit is set when the irq pin is asserted based on the irq mode.. the irq interrupt mask bit, imask, is used to enable or disable irq interrupt requests. 8.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 8.5.1 wait mode the irq module remains active in wait mode. clearing imask in in tscr enables irq interrupt requests to bring the mcu out of wait mode. 8.5.2 stop mode the irq module remains active in stop mode. clearing imask in in tscr enables irq interrupt requests to bring the mcu out of stop mode. 8.6 irq module duri ng break interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see bfcr in the sim section of this data sheet . to allow software to clear status bits during a break interrupt, write a 1 to bcfe. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to bcfe. with bcfe cleared (its default state), software can read and write registers during the break stat e without affecting status bits. some status bits have a two-step read/write clearing procedure. if softw are does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is cleared. after the break, doing the second step clears the status bit. 8.7 i/o signals the irq module does not share its pin with any module on this mcu. 8.7.1 irq input pins (irq ) the irq pin provides a maskable external interrupt source. the irq pin contains an internal pullup device.
registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 81 8.8 registers the irq status and control register (intscr) contro ls and monitors operation of the irq module. the intscr: shows the state of the irq flag clears the irq latch masks the irq interrupt request controls triggering sensitivity of the irq interrupt pin irqf ? irq flag bit this read-only status bit is set when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ? irq interrupt request acknowledge bit writing a 1 to this write-only bit clears the irq latch. ack always reads 0. imask ? irq interrupt mask bit writing a 1 to this read/write bit disables the irq interrupt request. 1 = irq interrupt request disabled 0 = irq interrupt request enabled mode ? irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. 1 = irq interrupt request on falling edges and low levels 0 = irq interrupt request on falling edges only bit 7654321bit 0 read:0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 8-3. irq status and control register (intscr)
external interrupt (irq) mc68hc908qb8 data sheet, rev. 1 82 freescale semiconductor
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 83 chapter 9 keyboard interrupt module (kbi) 9.1 introduction the keyboard interrupt module (kbi) provides independently maskable external interrupts. the kbi shares its pins with general-purpose input/output (i/o) port pins. see figure 9-1 for port location of these shared pins. 9.2 features features of the keyboard interrupt module include: keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask programmable edge-only or edge and level interrupt sensitivity edge sensitivity programmable for rising or falling edge level sensitivity programmable for high or low level pullup or pulldown device automatically enabled based on the polarity of edge or level detect exit from low-power modes 9.3 functional description the keyboard interrupt module controls the enabling/ disabling of interrupt functions on the kbi pins. these pins can be enabled/disabled independently of each other. see figure 9-2 . 9.3.1 keyboard operation writing to the kbiex bits in the keyboard inte rrupt enable register (kbier) independently enables or disables each kbi pin. the polarity of the keyboard interrupt is controlled using the kbipx bits in the keyboard interrupt polarity register (kbipr). edge-only or edge and level sensitivity is controlled using the modek bit in the keyboard status and control register (kbiscr). enabling a keyboard interrupt pin also enables its inte rnal pullup or pulldown device based on the polarity enabled. on falling edge or low level detection, a pullup device is configured. on rising edge or high level detection, a pulldown device is configured. the keyboard interrupt latch is set when one or more enabled keyboard interrupt inputs are asserted. if the keyboard interrupt sensitivity is edge-only, for kbipx = 0, a falling (for kbipx = 1, a rising) edge on a keyboard interrupt input does not latch an interrupt request if another enabled keyboard pin is already asserted. to pr event losing an interrupt request on one input because another input remains asserted, software can disable the latter input while it is asserted. if the keyboard interrupt is edge and level sensitiv e, an interrupt request is present as long as any enabled keyboard interrupt input is asserted.
keyboard interrupt module (kbi) mc68hc908qb8 data sheet, rev. 1 84 freescale semiconductor figure 9-1. block diagram highlighting kbi block and pins 9.3.1.1 modek = 1 if the modek bit is set, the keyboard interrupt inputs are both edge and level sensitive. the kbipx bit will determine whether a edge sensitive pin detects rising or falling edges and on level sensitive pins whether the pin detects low or high levels. with modek set, both of the following actions must occur to clear a keyboard interrupt request: return of all enabled keyboard interrupt inputs to a deasserted level. as long as any enabled keyboard interrupt pin is asserted, the keyboard interrupt remains active. rst , irq : pins have internal pull up device all port pins have pr ogrammable pull up device pta[0:5]: higher current sink and source capability pta0/tch0/ad0/kbi0 pta1/tch1/ad1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 4-channel 16-bit timer module keyboard interrupt module external interrupt module auto wakeup low-voltage inhibit cop module 10-channel 10-bit adc enhanced serial ptb0/sck/ad4 ptb ddrb m68hc08 cpu pta ddra ptb1/mosi/ad5 ptb2/miso/ad6 ptb3/ss /ad7 ptb4/rxd/ad8 ptb5/txd/ad9 ptb6/tch2 ptb7/tch3 power supply v dd v ss clock generator communications interface module module serial peripheral interface mc68hc908qb8 8192 bytes user flash 256 bytes user ram mc68hc908qb8 monitor rom break module development support
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 85 figure 9-2. keyboard interrupt block diagram vector fetch or software clear. a kbi vector fetc h generates an interrupt acknowledge signal to clear the kbi latch. software generates the interrupt acknowledge signal by writing a 1 to ackk in kbscr. the ackk bit is useful in applications th at poll the keyboard inte rrupt inputs and require software to clear the kbi latch. writing to ackk prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt inputs. an edge detect th at occurs after writing to ackk latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the kbi vector address. the kbi vector fetch or software clear and the return of all enabled keyboard interrupt pins to a deasserted level may occur in any order. reset clears the keyboard interrupt request and the mo dek bit, clearing the interrupt request even if a keyboard interrupt input stays asserted. 9.3.1.2 modek = 0 if the modek bit is clear, the keyboard interrupt inpu ts are edge sensitive. the kbipx bit will determine whether an edge sensitive pin detects rising or falling edges. a kbi vector fetch or software clear immediately clears the kbi latch. the keyboard flag bit (keyf) in kbscr can be read to check for pending interrupts. the keyf bit is not affected by imaskk, which makes it useful in applications wher e polling is preferred. note setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a 0 for software to read the pin. kbi latch keyboard interrupt request ackk internal bus reset kbie0 kbi0 0 1 s kbip0 kbiex kbix 0 1 s kbipx dq ck clr v dd modek imaskk synchronizer keyf to pullup/ to pullup/ pulldown enable pulldown enable vector fetch decoder awuireq (see figure 4-1 )
keyboard interrupt module (kbi) mc68hc908qb8 data sheet, rev. 1 86 freescale semiconductor 9.3.2 keyboard initialization when a keyboard interrupt pin is enabled, it takes time for the internal pullup or pulldown device to pull the pin to its deasserted level. therefore a false in terrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting imaskk in kbscr. 2. enable the kbi polarity by setting the appropriate kbipx bits in kbipr. 3. enable the kbi pins by setting the appropriate kbiex bits in kbier. 4. write to ackk in kbscr to clear any false interrupts. 5. clear imaskk. an interrupt signal on an edge sensitive pin can be acknowledged immediately after enabling the pin. an interrupt signal on an edge and level sensitive pin must be acknowledged after a delay that depends on the external load. 9.4 interrupts the following kbi source can generate interrupt requests: keyboard flag (keyf) ? the keyf bit is set w hen any enabled kbi pin is asserted based on the kbi mode and pin polarity. the keyboard interrupt ma sk bit, imaskk, is used to enable or disable kbi interrupt requests. 9.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 9.5.1 wait mode the kbi module remains active in wait mode. clearing imaskk in kbscr enab les keyboard interrupt requests to bring the mcu out of wait mode. 9.5.2 stop mode the kbi module remains active in stop mode. cl earing imaskk in kbscr enabl es keyboard interrupt requests to bring the mcu out of stop mode. 9.6 kbi during break interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see bfcr in the sim section of this data sheet . to allow software to clear status bits during a break interrupt, write a 1 to bcfe. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to bcfe. with bcfe cleared (its default state), software can read and write registers during the break stat e without affecting status bits. some status bits have a two-step read/write clearing procedure. if softw are does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is cleared. after the break, doing the second step clears the status bit.
i/o signals mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 87 9.7 i/o signals the kbi module can share its pins with the general-purpose i/o pins. see figure 9-1 for the port pins that are shared. 9.7.1 kbi input pins (kbix:kbi0) each kbi pin is independently programmable as an external interrupt source. kbi pin polarity can be controlled independently. each kbi pin w hen enabled will automatically configure the appropriate pullup/pulldown device based on polarity. 9.8 registers the following registers control and monitor operation of the kbi module: kbscr (keyboard interrupt status and control register) kbier (keyboard interrupt enable register) kbipr (keyboard interrupt polarity register) 9.8.1 keyboard status and control regi ster (kbscr) features of the kbscr: flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity bits 7?4 ? not used keyf ? keyboard flag bit this read-only bit is set when a keyboard interrupt is pending. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a 1 to this write-only bit clears the kbi request. ackk always reads 0. imaskk? keyboard interrupt mask bit writing a 1 to this read/write bit prevents the output of the kbi latch from generating interrupt requests. 1 = keyboard interrupt requests disabled 0 = keyboard interrupt requests enabled modek ? keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins. 1 = keyboard interrupt requests on edge and level 0 = keyboard interrupt requests on edge only bit 7654321bit 0 read:0000 keyf 0 imaskk modek write: ackk reset:00000000 = unimplemented figure 9-3. keyboard status and control register (kbscr)
keyboard interrupt module (kbi) mc68hc908qb8 data sheet, rev. 1 88 freescale semiconductor 9.8.2 keyboard interrupt enable regi ster (kbier) kbier enables or disables each keyboard interrupt pin. kbie5?kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corres ponding keyboard interrupt pin to latch kbi interrupt requests. 1 = kbix pin enabled as keyboard interrupt pin 0 = kbix pin not enabled as keyboard interrupt pin note awuie bit is not used in conjunction with the keyboard interrupt feature. to see a description of this bit, see chapter 4 auto wakeup module (awu) 9.8.3 keyboard interrupt po larity regist er (kbipr) kbipr determines the polarity of the enabled key board interrupt pin and enables the appropriate pullup or pulldown device. kbip5?kbip0 ? keyboard interrupt polarity bits each of these read/write bits enables the polarity of the keyboard interrupt detection. 1 = keyboard polarity is high level and/or rising edge 0 = keyboard polarity is low level and/or falling edge bit 7654321bit 0 read: 0 awuie kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 9-4. keyboard interrupt enable register (kbier) bit 7654321bit 0 read: 0 0 kbip5 kbip4 kbip3 kbip2 kbip1 kbip0 write: reset:00000000 = unimplemented figure 9-5. keyboard interrupt polarity register (kbipr)
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 89 chapter 10 low-voltage inhibit (lvi) 10.1 introduction the low-voltage inhibit (lvi) module is provided as a system protection mechanism to prevent the mcu from operating below a certain operating supply vo ltage level. the module has several configuration options to allow functionality to be tailo red to different system level demands. the configuration registers (see chapter 5 configuration register (config) ) contain control bits for this module. 10.2 features features of the lvi module include: programmable lvi reset selectable lvi trip voltage programmable stop mode operation 10.3 functional description figure 10-1 shows the structure of the lvi module. lvistop, lvipwrd, lvitrip, and lvirstd are user selectable options found in the configuration register. figure 10-1. lvi module block diagram low v dd detector lvipwrd stop instruction lvistop lvi reset lviout 0 if v dd > v tripr 1 if v dd v tripf from configuration register v dd lvirstd lvitrip from configuration register from configuration register from configuration register
low-voltage inhibit (lvi) mc68hc908qb8 data sheet, rev. 1 90 freescale semiconductor the lvi module contains a bandgap reference circui t and comparator. when the lvitrip bit is cleared, the default state at power-on reset, v tripf is configured for the lower v dd operating range. the actual trip points are specified in 18.5 5-v dc electrical characteristics and 18.8 3-v dc electrical characteristics . because the default lvi trip point after power-on rese t is configured for low voltage operation, a system requiring high voltage lvi operation must set t he lvitrip bit during system initialization. v dd must be above the lvi trip rising voltage, v tripr , for the high voltage operating range or the mcu will immediately go into lvi reset. after an lvi reset occurs, the mcu remains in reset until v dd rises above v tripr . see chapter 14 system integration module (sim) for the reset recovery sequence. the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr) and can be used for polling lvi operat ion when the lvi reset is disabled. the lvi is enabled out of reset. the following bits located in the configuration register can alter the default conditions. setting the lvi power disable bit, lvipwrd, disables the lvi. setting the lvi reset disable bit, lvirstd, pr events the lvi module from generating a reset. setting the lvi enable in stop mode bit, lvistop, enables the lvi to operate in stop mode. setting the lvi trip point bit, lvitrip, configures the trip point voltage (v tripf ) for the higher v dd operating range. 10.3.1 polled lvi operation in applications that can operate at v dd levels below the v tripf level, software can monitor v dd by polling the lviout bit. in the configuration register, lvip wrd must be cleared to enable the lvi module, and lvirstd must be set to disable lvi resets. 10.3.2 forced reset operation in applications that require v dd to remain above the v tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls below the v tripf level. in the configuration register, lvipwrd and lvirstd must be cleared to enable the lvi module and to enable lvi resets. 10.3.3 lvi hysteresis the lvi has hysteresis to maintain a stable operat ing condition. after the lvi has triggered (by having v dd fall below v tripf ), the mcu will remain in reset until v dd rises above the rising trip point voltage, v tripr . this prevents a condition in which the mcu is continually entering and exiting reset if v dd is approximately equal to v tripf . v tripr is greater than v tripf by the typical hysteresis voltage, v hys . 10.3.4 lvi trip selection lvitrip in the configuration register selects the lv i protection range. the default setting out of reset is for the low voltage range. because lvitrip is in a write-once configuration register, the protection range cannot be changed after initialization. note the mcu is guaranteed to operate at a minimum supply voltage. the trip point (v tripf ) may be lower than this. see the electrical characteristics section for the actual trip point voltages.
lvi interrupts mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 91 10.4 lvi interrupts the lvi module does not generate interrupt requests. 10.5 low-power modes the stop and wait instructions put the mcu in low power-consumption standby modes. 10.5.1 wait mode if enabled, the lvi module remains active in wait m ode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. 10.5.2 stop mode if the lvipwrd bit in the configuration register is cleared and the lvistop bit in the configuration register is set, the lvi module remains active. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode. 10.6 registers the lvi status register (lvisr) contains a status bit that is useful when the lvi is enabled and lvi reset is disabled. lviout ? lvi output bit this read-only flag becomes set when the v dd voltage falls below the v tripf trip voltage and is cleared when v dd voltage rises above v tripr . (see table 10-1 ). bit 76 5 4 3 2 1bit 0 read:lviout000000r write: reset:00000000 = unimplemented r = reserved figure 10-2. lvi status register (lvisr) table 10-1. lviout bit indication v dd lviout v dd > v tripr 0 v dd < v tripf 1 v tripf < v dd < v tripr previous value
low-voltage inhibit (lvi) mc68hc908qb8 data sheet, rev. 1 92 freescale semiconductor
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 93 chapter 11 oscillator module (osc) 11.1 introduction the oscillator (osc) module is used to provide a stable clock source for the mcu system and bus. the osc shares its pins with general-pur pose input/output (i/o) port pins. see figure 11-1 for port location of these shared pins. the osc2en bit is located in the por t a pull enable register (ptapuen) on this mcu. see chapter 12 input/output ports (ports) for information on ptapuen register. 11.2 features the bus clock frequency is one fourth of any of these clock source options: 1. internal oscillator: an internally gener ated, fixed frequency clock, trimmable to 0.4%. there are three choices for the internal oscillator,12.8 mhz, 8 mhz, or 4 mhz. the 4-mhz internal oscillator is the default option out of reset. 2. external oscillator: an external clock that can be driven di rectly into osc1. 3. external rc: a built-in oscillator module (rc os cillator) that requires an external r connection only. the capacitor is internal to the chip. 4. external crystal: a built-in xtal oscillator that requires an external crystal or ceramic-resonator. there are three crystal frequency ranges su pported, 8?32 mhz, 1?8 mhz, and 32?100 khz. 11.3 functional description the oscillator contains these major subsystems: internal oscillator circuit internal or external clock switch control external clock circuit external crystal circuit external rc clock circuit
oscillator module (osc) mc68hc908qb8 data sheet, rev. 1 94 freescale semiconductor figure 11-1. block diagram highlighting osc block and pins rst , irq : pins have internal pull up device all port pins have prog rammable pull up device pta[0:5]: higher current sink and source capability pta0/tch0/ad0/kbi0 pta1/tch1/ad1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 4-channel 16-bit timer module keyboard interrupt module external interrupt module auto wakeup low-voltage inhibit cop module 10-channel 10-bit adc enhanced serial ptb0/sck/ad4 ptb ddrb m68hc08 cpu pta ddra ptb1/mosi/ad5 ptb2/miso/ad6 ptb3/ss /ad7 ptb4/rxd/ad8 ptb5/txd/ad9 ptb6/tch2 ptb7/tch3 power supply v dd v ss clock generator communications interface module module serial peripheral interface mc68hc908qb8 8192 bytes user flash 256 bytes user ram mc68hc908qb8 monitor rom break module development support
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 95 11.3.1 internal signal definitions the following signals and clocks are used in the f unctional description and figures of the osc module. 11.3.1.1 oscillator enable signal (simoscen) the simoscen signal comes from the system integrat ion module (sim) and disables the xtal oscillator circuit, the rc oscillator, or the internal oscillat or in stop mode. osceninstop in the configuration register can be used to override this signal. 11.3.1.2 xtal oscillator clock (xtalclk) xtalclk is the xtal oscillator output signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 11-2 shows only the logical relation of xtalclk to osc1 and osc2 and may not represent the actual circui try. the duty cycle of xtalclk is unknown and may depend on the crystal and other external factors. the frequency of xtalclk can be unstable at start up. 11.3.1.3 rc oscillator clock (rcclk) rcclk is the rc oscillator output signal. its frequency is directly proportional to the time constant of the external r (r ext ) and internal c. figure 11-3 shows only the logical relation of rcclk to osc1 and may not represent the actual circuitry. 11.3.1.4 internal oscillator clock (intclk) intclk is the internal oscillator output signal. intc lk is software selectable to be nominally 12.8 mhz, 8.0 mhz, or 4.0 mhz. intclk can be digitally ad justed using the oscillator trimming feature of the osctrim register (see 11.3.2.1 internal oscillator trimming ). 11.3.1.5 bus clock times 4 (busclkx4) busclkx4 is the same frequency as the input cloc k (xtalclk, rcclk, or intclk). this signal is driven to the sim module and is used during recovery from reset and stop and is the clock source for the cop module. 11.3.1.6 bus clock times 2 (busclkx2) the frequency of this signal is equal to half of the busclkx4. this signal is driven to the sim for generation of the bus clocks used by the cpu and other modules on the mcu. busclkx2 will be divided by two in the sim. the internal bus frequency is one fourth of the xtalclk, rcclk, or intclk frequency. 11.3.2 internal oscillator the internal oscillator circuit is designed for use wi th no external components to provide a clock source with a tolerance of less than 25% untrimmed. an 8- bit register (osctrim) allo ws the digital adjustment to a tolerance of acc int . see the oscillator characteristics in th e electrical section of this data sheet. the internal oscillator is capabl e of generating clocks of 12.8 mhz, 8.0 mhz, or 4.0 mhz (intclk) resulting in a bus frequency (intclk divided by 4) of 3.2 mhz, 2.0 mhz, or 1.0 mhz respectively. the bus clock is software selectable and defaults to th e 1.0-mhz bus out of reset. users can increase the bus frequency based on the voltage range of their application.
oscillator module (osc) mc68hc908qb8 data sheet, rev. 1 96 freescale semiconductor figure 11-3 shows how busclkx4 is derived from intc lk and osc2 can output busclkx4 by setting osc2en. 11.3.2.1 internal oscillator trimming osctrim allows a clock period adjustment of +127 and ?128 steps. increasing the osctrim value increases the clock period, which decreases the cl ock frequency. trimming allo ws the internal clock frequency to be fine tuned to the target frequency. all devices are factory programmed with a trim value that is stored in flash memory at location $ffc0. this trim value is not automatically loaded into osctrim register. user software must copy the trim value from $ffc0 into osctrim if needed. the factory trim value provides the accuracy required for communication using force monitor m ode. trimming the device in the user application board will provide the most accurate trim value. see oscillator characteri stics in the electrical chapter of this data book for additional information on factory trim. 11.3.2.2 internal to external clock switching when external clock source (external osc, rc, or xtal) is desired, the user must perform the following steps: 1. for external crystal circuits onl y, configure oscopt[1:0] to external crystal. to help precharge an external crystal oscillator, momentarily configur e osc2 as an output and drive it high for several cycles. this can help the crysta l circuit start more robustly. 2. configure oscopt[1:0] and ecfs[1:0] according to 11.8.1 oscillator status and control register . the oscillator module control logic will then ena ble osc1 as an external clock input and, if the external crystal option is selected, osc2 will also be enabled as the clock output. if rc oscillator option is selected, enabling the osc2 output may change the bus frequency. 3. create a software delay to provide the stabilization time required for the selected clock source (crystal, resonator, rc). a good rule of thumb for crystal oscillators is to wait 4096 cycles of the crystal frequency; i.e., for a 4-mhz crystal, wait approximately 1 ms. 4. after the stabilization delay has elapsed, set ecgon. after ecgon set is detected, the osc module checks for oscillator activity by waiting two external clock rising edges. the osc module then switches to the ex ternal clock. logic provi des a coherent transition. the osc module first sets ecgst and th en stops the internal oscillator. 11.3.2.3 external to internal clock switching after following the procedures to switch to an external clock source, it is possible to go back to the internal source. by clearing the oscopt[1:0] bits and clear ing the ecgon bit, the external circuit will be disengaged. the bus clock will be derived from the se lected internal clock source based on the icfs[1:0] bits. 11.3.3 external oscillator the external oscillator option is designed for use when a clock signal is available in the application to provide a clock source to the mcu. the osc1 pin is enabled as an input by the oscillator module. the clock signal is used directly to create busclkx4 and also divided by two to create busclkx2. in this configuration, the osc2 pin cannot output busclkx4. the osc2en bit will be forced clear to enable alternative functions on the pin.
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 97 11.3.4 xtal oscillator the xtal oscillator circuit is designed for use with an external crystal or cera mic resonator to provide an accurate clock source. in this configuration, the osc2 pin is dedicated to the external crystal circuit. the osc2en bit has no effect when this clock mode is selected. in its typical configuration, the xtal oscillator is conn ected in a pierce oscillator configuration, as shown in figure 11-2 . this figure shows only the logical repres entation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) note the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be r equired for all ranges of operation, especially with high frequency crystals. refer to the oscillator characteristics table in the electr icals section for more information. figure 11-2. xtal oscillator external connections c 1 c 2 xtalclk r b x 1 r s mcu osc2 osc1 2 busclkx2 busclkx4 see the electrical section for details. simoscen (internal signal) or osceninstop (bit located in configuration register)
oscillator module (osc) mc68hc908qb8 data sheet, rev. 1 98 freescale semiconductor 11.3.5 rc oscillator the rc oscillator circuit is designed for use with an external resistor (r ext ) to provide a clock source with a tolerance within 25% of the expected frequency. see figure 11-3 . the capacitor (c) for the rc oscillator is internal to the mcu. the r ext value must have a tolerance of 1% or less to minimize its effect on the frequency. in this configuration, the osc2 pin can be used as general-purpose input/output (i/o) port pins or other alternative pin function. the osc2en bit can be se t to enable the osc2 output function on the pin. enabling the osc2 output can affect the external rc oscillator frequency, f rcclk . figure 11-3. rc oscillator external connections 11.4 interrupts there are no interrupts associated with the osc module. 11.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 11.5.1 wait mode the osc module remains active in wait mode. 11.5.2 stop mode the osc module can be configured to remain active in stop mode by setting osceninstop located in a configuration register. mcu r ext osc1 external rc oscillator en rcclk 2 busclkx2 busclkx4 v dd 1 0 osc2en osc2 ? available for alternative pin function see the electricals section for component value. 0 1 intclk oscopt = external rc selected simoscen (internal signal) or osceninstop (bit located in configuration register) alternative pin funtion
osc during break interrupts mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 99 11.6 osc during break interrupts there are no status flags associated with the osc module. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see bfcr in the sim section of this data sheet . to allow software to clear status bits during a break interrupt, write a 1 to bcfe. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to bcfe. with bcfe cleared (its default state), software can read and write registers during the break stat e without affecting status bits. some status bits have a two-step read/write clearing procedure. if softw are does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is cleared. after the break, doing the second step clears the status bit. 11.7 i/o signals the osc shares its pins with general-pur pose input/output (i/o) port pins. see figure 11-1 for port location of these shared pins. 11.7.1 oscillator input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifie r, an input to the rc oscillator circuit, or an input from an external clock source. when the osc is configured for internal oscillat or, the osc1 pin can be used as a general-purpose input/output (i/o) port pin or other alternative pin function. 11.7.2 oscillator output pin (osc2) for the xtal oscillator option , the osc2 pin is the output of the crystal oscillator amplifier. when the osc is configured for internal oscillator, external clock, or rc, the osc2 pin can be used as a general-purpose i/o port pin or other alternative pin fu nction. when the oscillator is configured for internal or rc, the osc2 pin can be used to output busclkx4. table 11-1. osc2 pin function option osc2 pin function xtal oscillator inverting osc1 external clock general-purpose i/o or alternative pin function internal oscillator or rc oscillator controlled by osc2en bit osc2en = 0: general-purpose i/o or alternative pin function osc2en = 1: busclkx4 output
oscillator module (osc) mc68hc908qb8 data sheet, rev. 1 100 freescale semiconductor 11.8 registers the oscillator module contains two registers: oscillator status and c ontrol register (oscsc) oscillator trim register (osctrim) 11.8.1 oscillator st atus and control register the oscillator status and control register (oscsc) contains the bits for switching between internal and external clock sources. if the application uses an external crystal, bits in this register are used to select the crystal oscillator amplifier necessary for the desire d crystal. while running off the internal clock source, the user can use bits in this register to select the internal clock source frequency. oscopt1:oscopt0 ? osc option bits these read/write bits allow the user to change the clock source for the mcu. the default reset condition has the bus clock being derived from the internal oscillator. see 11.3.2.2 internal to external clock switching for information on changing clock sources. icfs1:icfs0 ? internal clock frequency select bits these read/write bits enable the frequency to be increas ed for applications requiring a faster bus clock when running off the internal oscillator. the wait instruction has no effect on the oscillator logic. busclkx2 and busclkx4 continue to drive to the sim module. bit 7654321bit 0 read: oscopt1 oscopt0 icfs1 icfs0 ecfs1 ecfs0 ecgon ecgst write: reset:0 0000000 = unimplemented figure 11-4. oscillator status and control register (oscsc) oscopt1 oscopt0 oscillator modes 0 0 internal oscillator (frequency selected using icfsx bits) 0 1 external oscillator clock 10external rc 1 1 external crystal (range selected using ecfsx bits) icfs1 icfs0 internal clock frequency 0 0 4.0 mhz ? default reset condition 0 1 8.0 mhz 1 0 12.8 mhz 11reserved
registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 101 ecfs1:ecfs0 ? external crystal frequency select bits these read/write bits enable the specific amplifier for the crystal frequency range. refer to oscillator characteristics table in the electricals section fo r information on maximum external clock frequency versus supply voltage. ecgon ? external clock generator on bit this read/write bit enables the osc1 pin as the cloc k input to the mcu, so that the switching process can be initiated. this bit is cleared by reset. this bit is ignored in monitor mode with the internal oscillator bypassed. 1 = external clock enabled 0 = external clock disabled ecgst ? external clock status bit this read-only bit indicates whether an external clock source is engaged to drive the system clock. 1 = an external clock source engaged 0 = an external clock source disengaged 11.8.2 oscillator tr im register (osctrim) trim7?trim0 ? internal oscillator trim factor bits these read/write bits change the internal capacitanc e used by the internal oscillator. by measuring the period of the internal clock and adjusting this factor accordingly, the frequency of the internal clock can be fine tuned. increasing (decreasing) this fact or by one increases (decreases) the period by approximately 0.2% of the untrimmed oscillator period. the oscillator period is based on the oscillator frequency selected by the icfs bits in oscsc. ecfs1 ecfs0 external crystal frequency 0 0 8 mhz ? 32 mhz 0 1 1 mhz ? 8 mhz 1 0 32 khz ? 100 khz 11reserved bit 7654321bit 0 read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 figure 11-5. oscillator trim register (osctrim)
oscillator module (osc) mc68hc908qb8 data sheet, rev. 1 102 freescale semiconductor
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 103 chapter 12 input/output ports (ports) 12.1 introduction the mc68hc908qb8, MC68HC908QB4 and mc68hc908qy8 have thirteen bidirectional pins and one input only pin. note connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. 12.2 port a port a is an 6-bit special function port that shares its pins with the keyboard interrupt (kbi) module (see chapter 9 keyboard interrupt module (kbi) , the 4-channel timer interface module (tim) (see chapter 16 timer interface module (tim) ), the 10-bit adc (see chapter 3 analog-to-digital converter (adc10) module ), the external interrupt (irq) pin (see chapter 8 external interrupt (irq) ), the reset (rst) pin enabled using a configuration register (see chapter 5 configuration register (config) ) and the oscillator pins (see chapter 11 oscillator module (osc) ). each port a pin also has a software configurable pullup device if the co rresponding port pin is configured as an input port. note pta2 is input only. when the irq function is enabled in the configuration register 2 (config2), bit 2 of the port a data register (pta) will always read a logic 0. in this case, the bih and bil instructi ons can be used to read the logic level on the pta2 pin. when the irq function is disabled, these instructions will behave as if the pta2 pin is a logic 1. however, reading bit 2 of pta will read the actual logic level on the pin.
input/output ports (ports) mc68hc908qb8 data sheet, rev. 1 104 freescale semiconductor 12.2.1 port a data register the port a data register (pta) contains a data latch for each of the six port a pins. pta[5:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction regi ster a. reset has no effect on port a data. awul ? auto wakeup latch data bit this is a read-only bit which has the value of the auto wakeup interrupt request latch. the wakeup request signal is generated internally (see chapter 4 auto wakeup module (awu) ). there is no pta6 port nor any of the associated bits such as pt a6 data register, pullup enable or direction. . 12.2.2 data dir ection register a data direction register a (ddra) determines whether eac h port a pin is an input or an output. writing a 1 to a ddra bit enables the output buffer for the co rresponding port a pin; a 0 disables the output buffer. ddra[5:0] ? data direction register a bits these read/write bits contro l port a data direction. reset clears ddra[5:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note avoid glitches on port a pins by writin g to the port a data register before changing data direction regist er a bits from 0 to 1. figure 12-3 shows the port a i/o logic. bit 76 5 4 3 2 1bit 0 read: r awul pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset = unimplemented figure 12-1. port a data register (pta) bit 7654321bit 0 read: r r ddra5 ddra4 ddra3 0 ddra1 ddra0 write: reset:00000000 r= reserved = unimplemented figure 12-2. data direction register a (ddra)
port a mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 105 figure 12-3. port a i/o circuit note figure 12-3 does not apply to pta2 when ddrax is a 1, reading pta reads the ptax dat a latch. when ddrax is a 0, reading pta reads the logic level on the ptax pin. the data latch can always be written, regardless of the state of its data direction bit. 12.2.3 port a input pullup enable register the port a input pullup enable register (ptapue) cont ains a software configur able pullup device for each of the port a pins. each bit is individually c onfigurable and requires the corresponding data direction register, ddrax, to be configured as input. each pu llup device is automatically and dynamically disabled when its corresponding ddrax bit is configured as output. osc2en ? enable pta4 on osc2 pin this read/write bit configures the osc2 pin function when internal oscillator or rc oscillator option is selected. this bit has no effect for the xtal or external oscillator options. 1 = osc2 pin outputs the internal or rc oscillator clock (busclkx4) 0 = osc2 pin configured for pta4 i/o, hav ing all the interrupt and pullup functions ptapue[5:0] ? port a input pullup enable bits these read/write bits are software programma ble to enable pullup devices on port a pins. 1 = corresponding port a pin configured to have in ternal pullup if its ddra bit is set to 0 0 = pullup device is disconnected on the corresponding port a pin regardless of the state of its ddra bit bit 7654321bit 0 read: osc2en ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 = unimplemented figure 12-4. port a input pullup enable register (ptapue) read ddra write ddra reset write pta read pta ptax ddrax ptax internal data bus pullup ptapuex
input/output ports (ports) mc68hc908qb8 data sheet, rev. 1 106 freescale semiconductor 12.2.4 port a summary table the following table summarizes the operation of the port a pins when used as a general-purpose input/output pins. 12.3 port b port b is an 8-bit special function port that shares it s pins with the 4-channel ti mer interface module (tim) (see chapter 16 timer interface module (tim) ), the 10-bit adc (see chapter 3 analog-to-digital converter (adc10) module ), the serial peripheral interface (spi) module (see chapter 15 serial peripheral interface (spi) module ) and the enhanced serial communications interface (esci) module (see chapter 13 enhanced serial communi cations interface (esci) module ). each port b pin also has a software configurable pullup device if the co rresponding port pin is configured as an input port. 12.3.1 port b data register the port b data register (ptb) contains a data latch for each of the port b pins. ptb[7:0] ? port b data bits these read/write bits are software programmable. data direction of each port b pin is under the control of the corresponding bit in data direction regi ster b. reset has no effect on port b data. table 12-1. port a pin functions ptapue bit ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 10 x (1) 1. x = don?t care input, v dd (2) 2. i/o pin pulled to v dd by internal pullup. ddra5?ddra0 pin pta5?pta0 (3) 3. writing affects data regist er, but does not affect input. 00x input, hi-z (4) 4. hi-z = high impedance ddra5?ddra0 pin pta5?pta0 (3) x 1 x output ddra5?ddra0 pta5?pta0 pta5?pta0 (5) 5. output does not apply to pta2 bit 76 5 4 3 2 1bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset figure 12-5. port b data register (ptb)
port b mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 107 12.3.2 data dir ection register b data direction register b (ddrb) determines whether eac h port b pin is an input or an output. writing a 1 to a ddrb bit enables the output buffer for the co rresponding port b pin; a 0 disables the output buffer. ddrb[7:0] ? data direction register b bits these read/write bits contro l port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note avoid glitches on port b pins by writin g to the port b data register before changing data direction regist er b bits from 0 to 1. figure 12-7 shows the port b i/o logic. figure 12-7. port b i/o circuit when ddrbx is a 1, reading ptb reads the ptbx dat a latch. when ddrbx is a 0, reading ptb reads the logic level on the ptbx pin. the data latch can always be written, regardless of the state of its data direction bit. bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 12-6. data direction register b (ddrb) read ddrb write ddrb reset write ptb read ptb ptbx ddrbx ptbx internal data bus pullup ptbpuex
input/output ports (ports) mc68hc908qb8 data sheet, rev. 1 108 freescale semiconductor 12.3.3 port b input pullup enable register the port b input pullup enable register (ptbpue) cont ains a software configur able pullup device for each of the eight port b pins. each bit is individually co nfigurable and requires the corresponding data direction register, ddrbx, be configured as input. each pullup device is automatically and dynamically disabled when its corresponding ddrbx bit is configured as output. ptbpue[7:0] ? port b input pullup enable bits these read/write bits are software programma ble to enable pullup devices on port b pins 1 = corresponding port b pin configured to have internal pull if its ddrb bit is set to 0 0 = pullup device is disconnected on the corresponding port b pin regardless of the state of its ddrb bit. 12.3.4 port b summary table table 12-2 summarizes the operation of the port a pins when used as a general-purpose input/output pins. bit 7654321bit 0 read: ptbpue7 ptbpue6 ptbpue5 ptbpue4 ptbpue3 ptbpue2 ptbpue2 ptbpue0 write: reset:00000000 figure 12-8. port b input pullup enable register (ptbpue) table 12-2. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrb7?ddrb0 pin ptb7?ptb0 (3) 3. writing affects data register, but does not affect the input. 1 x output ddrb7?ddrb0 pin ptb7?ptb0
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 109 chapter 13 enhanced serial communications interface (esci) module 13.1 introduction the enhanced serial communications interface (esc i) module allows asynchronous communications with peripheral devices and other microcontroller units (mcu). the esci module shares its pins with general -purpose input/output (i/o) port pins. see figure 13-1 for port location of these shared pins. the esci baud ra te clock source is controlled by a bit (scibdsrc) located in the configuration register. 13.2 features features include: full-duplex operation standard mark/space non-retu rn-to-zero (nrz) format programmable baud rates programmable 8-bit or 9-bit character length separately enabled transmitter and receiver separate receiver and transmitter interrupt requests programmable transmitter output polarity receiver wakeup methods ? idle line ? address mark interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framing error detection hardware parity checking 1/16 bit-time noise detection
enhanced serial communicatio ns interface (esci) module mc68hc908qb8 data sheet, rev. 1 110 freescale semiconductor figure 13-1. block diagram highlighting esci block and pins rst , irq : pins have internal pull up device all port pins have prog rammable pull up device pta[0:5]: higher current sink and source capability pta0/tch0/ad0/kbi0 pta1/tch1/ad1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 4-channel 16-bit timer module keyboard interrupt module external interrupt module auto wakeup low-voltage inhibit cop module 10-channel 10-bit adc enhanced serial ptb0/sck/ad4 ptb ddrb m68hc08 cpu pta ddra ptb1/mosi/ad5 ptb2/miso/ad6 ptb3/ss /ad7 ptb4/rxd/ad8 ptb5/txd/ad9 ptb6/tch2 ptb7/tch3 power supply v dd v ss clock generator communications interface module module serial peripheral interface mc68hc908qb8 8192 bytes user flash 256 bytes user ram mc68hc908qb8 monitor rom break module development support
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 111 13.3 functional description figure 13-2 shows the structure of the esci module. t he esci allows full-duplex, asynchronous, nrz serial communication between the mcu and remote dev ices, including other mcus. the transmitter and receiver of the esci operate independently, alt hough they use the same baud rate generator. figure 13-2. esci module block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 orie feie peie bkf rpf esci data receive shift register esci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register transmitter interrupt control receiver interrupt control error interrupt control control ensci loops ensci internal bus txinv loops 4 16 pre- scaler baud rate generator scibdsrc rxd txd arbiter sci_txd rxd linr lint bus_clk aclk bit in sciactl sl sci_clk enhanced prescaler sl from config bus cgmxclk clock sl = 1 -> sci_clk = busclk sl = 0 -> sci_clk = cgmxclk (4x busclk) fegister
enhanced serial communicatio ns interface (esci) module mc68hc908qb8 data sheet, rev. 1 112 freescale semiconductor 13.3.1 data format the sci uses the standard mark/space non-return-to-zero (nrz) format illustrated in figure 13-3 . figure 13-3. sci data formats 13.3.2 transmitter figure 13-4 shows the structure of the sci transmitter. figure 13-4. esci transmitter bit 5 bit 0 bit 1 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 parity or data bit parity or data bit next start bit next start bit stop bit stop bit 8-bit data format (bit m in scc1 clear) 9-bit data format (bit m in scc1 set) start bit start bit pen pty stop876543210start 11-bit transmit t8 scte sctie tcie sbk tc parity generation msb esci data register load from scdr shift enable preamble (all ones) break (all zeros) transmitter control logic shift register tc sctie tcie scte m ensci loops te txinv internal bus 4 pre- scaler scp1 scp0 scr1 scr2 scr0 baud divider 16 sci_txd pre- scaler pds1 pds2 pds0 pssb3 pssb4 pssb2 pssb1 pssb0 lint transmitter interrupt request cgmxclk or bus clock
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 113 13.3.2.1 character length the transmitter can accommodate either 8-bit or 9- bit data. the state of the m bit in esci control register 1 (scc1) determines character length. when tr ansmitting 9-bit data, bit t8 in esci control register 3 (scc3) is the ninth bit (bit 8). 13.3.2.2 character transmission during an esci transmission, the transmit shift regist er shifts a character out to the txd pin. the esci data register (scdr) is the write-only buffer between t he internal data bus and the transmit shift register. to initiate an esci transmission: 1. enable the esci by writing a 1 to the enable esci bit (ensci) in esci control register 1 (scc1). 2. enable the transmitter by writing a 1 to the trans mitter enable bit (te) in esci control register 2 (scc2). 3. clear the esci transmitter empty bit (scte) by first reading esci status register 1 (scs1) and then writing to the scdr. for 9-bit data, also write the t8 bit in scc3. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, transmitter control logi c automatically loads the tran smit shift register with a preamble of 1s. after the preamble shifts out, cont rol logic transfers the s cdr data into the transmit shift register. a 0 start bit automatically goes into the least significant bit (lsb) position of the transmit shift register. a 1 stop bit goes into the most significant bit (msb) position. the esci transmitter empty bit, scte, in scs1 beco mes set when the scdr transfers a byte to the transmit shift register. the scte bi t indicates that the scdr can accept new data from the internal data bus. if the esci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmitter interrupt request. when the transmit shift register is not transmitting a c haracter, the txd pin goes to the idle condition, high. if at any time software clears the ensc i bit in esci control register 1 (scc1), the transmitter and receiver relinquish control of the port pins. 13.3.2.3 break characters writing a 1 to the send break bit, sbk, in scc2 loads the transmit shift register with a break character. for txinv = 0 (output not inverted), a transmitted break character contains all 0s and has no start, stop, or parity bit. break character length depends on the m bit in scc1 and the linr bits in scbr. as long as sbk is set, transmitter logic continuously loads break characters into the transmit shift register. after software clears the sbk bit, the shift register finis hes transmitting the last break character and then transmits at least one 1. the automatic 1 at the end of a break character guarantees the recognition of the start bit of the next character. when linr is cleared in scbr, the esci recognizes a break character when a start bit is followed by eight or nine 0 data bits and a 0 where the stop bit shoul d be, resulting in a total of 10 or 11 consecutive 0 data bits. when linr is set in scbr, the esci recognizes a break character when a start bit is followed by 9 or 10 0 data bits and a 0 where the stop bit shoul d be, resulting in a total of 11 or 12 consecutive 0 data bits.
enhanced serial communicatio ns interface (esci) module mc68hc908qb8 data sheet, rev. 1 114 freescale semiconductor receiving a break character has these effects on esci registers: sets the framing error bit (fe) in scs1 sets the esci receiver full bit (scrf) in scs1 clears the esci data register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception in progress flag (rpf) bits 13.3.2.4 idle characters for txinv = 0 (output not inverted), a transmitted idle character contains all 1s and has no start, stop, or parity bit. idle character length depends on the m bi t in scc1. the preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a transmission, the txd pin become s idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the character currently being transmitted. 13.3.2.5 inversion of transmitted output the transmit inversion bit (txinv) in esci control r egister 1 (scc1) reverses the polarity of transmitted data. all transmitted values including idle, break, st art, and stop bits, are inverted when txinv is set. see 13.8.1 esci control register 1 . 13.3.3 receiver figure 13-5 shows the structure of the esci receiver. 13.3.3.1 character length the receiver can accommodate either 8-bit or 9-bit dat a. the state of the m bit in esci control register 1 (scc1) determines character length. when receiving 9-bi t data, bit r8 in esci control register 3 (scc3) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 13.3.3.2 character reception during an esci reception, the receive shift register sh ifts characters in from the rxd pin. the esci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive sh ift register, the data portion of the character transfers to the scdr. the esci receiver full bit, scrf, in esci status register 1 (scs1) becomes set, indicating that the received byte can be read. if the esci rece ive interrupt enable bit, scrie, in scc2 is also set, the scrf bit generates a receiver interrupt request.
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 115 figure 13-5. esci receiver block diagram all ones all zeros m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery or orie nf neie fe feie pe peie scrie scrf ilie idle wakeup logic parity checking msb esci data register r8 scrie ilie rwu scrf idle internal bus pre- scaler baud divider 4 16 scp1 scp0 scr1 scr2 scr0 rxd pre- scaler pds1 pds2 pds0 pssb3 pssb4 pssb2 pssb1 pssb0 linr orie neie feie peie or nf fe pe cgmxclk or bus clock interrupt request error interrupt receiver request
enhanced serial communicatio ns interface (esci) module mc68hc908qb8 data sheet, rev. 1 116 freescale semiconductor 13.3.3.3 data sampling the receiver samples the rxd pin at the rt clock rate . the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at these times (see figure 13-6 ): after every start bit after the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid 0) to locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s. when the falling edge of a possible start bit oc curs, the rt clock begins to count to 16. figure 13-6. receiver data sampling to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 13-1 summarizes the results of the start bit verification samples. if start bit verification is not successful, the rt cl ock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 13-2 summarizes the results of the data bit samples. table 13-1. start bit verification rt3, rt5, and rt7 samples sta rt bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb rxd
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 117 note the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are 1s following a successful start bit verification, the noi se flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 13-3 summarizes the results of the stop bit samples. 13.3.3.4 framing errors if the data recovery logic does not detect a 1 where t he stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. a break character also sets the fe bit because a break character has no stop bit. the fe bit is set at t he same time that the scrf bit is set. 13.3.3.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bi t data samples to fall outside the actual stop bit. then a noise error occurs. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within char acters corrects misalignments between transmitter bit times and receiver bit times. table 13-2. data bit recovery rt8, rt9, and rt10 samples d ata bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 13-3. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0
enhanced serial communicatio ns interface (esci) module mc68hc908qb8 data sheet, rev. 1 118 freescale semiconductor slow data tolerance figure 13-7 shows how much a slow received character can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 inst ead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 13-7. slow data for an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times 16 rt cycles +10rtcycles=154rtcycles. with the misaligned character shown in figure 13-7 , the receiver counts 154 rt cycles at the point when the count of the transmitti ng device is 9 bit times 16 rt cycles + 3 rt cycles = 147 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is: for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles +10rtcycles=170rtcycles. with the misaligned character shown in figure 13-7 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles + 3 rt cycles = 163 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: fast data tolerance figure 13-8 shows how much a fast received character can be misaligned without causing a noise error or a framing error. the fast stop bit ends at rt10 instead of rt16 but is still there for the stop bit data samples at rt8, rt9, and rt10. figure 13-8. fast data msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 147 ? 154 ------------------------- - 100 4.54% = 170 163 ? 170 ------------------------- - 100 4.12% = idle or next character stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock
interrupts mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 119 for an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times 16 rt cycles +10rtcycles=154rtcycles. with the misaligned character shown in figure 13-8 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is for a 9-bit character, data sampling of t he stop bit takes the receiver 10 bit times 16 rt cycles +10rtcycles=170rtcycles. with the misaligned character shown in figure 13-8 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 11 bit times 16 rt cycles = 176 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: 13.3.3.6 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in scc2 puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bi t in scc1, either of two conditio ns on the rxd pin can bring the receiver out of the standby state: 1. address mark ? an address mark is a 1 in th e msb position of a received character. when the wake bit is set, an address mark wakes the receiv er from the standby st ate by clearing the rwu bit. the address mark also sets the esci receiver full bit, scrf. software can then compare the character containing the address mark to the user -defined address of the receiver. if they are the same, the receiver remains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. 2. idle input line condition ? when the wake bit is cl ear, an idle character on the rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the esci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting 1s as idle character bits after the start bit or after the stop bit. note with the wake bit clear, setting the rwu bit after the rxd pin has been idle will cause the receiver to wake up. 13.4 interrupts the following sources can generate esci interrupt requests. 154 160 ? 154 ------------------------- - 100 3.90%. = 170 176 ? 170 ------------------------- - 100 3.53%. =
enhanced serial communicatio ns interface (esci) module mc68hc908qb8 data sheet, rev. 1 120 freescale semiconductor 13.4.1 transmit ter interrupts these conditions can generate interrupt requests from the esci transmitter: esci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can generate a transmitter interrupt request. setting the esci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generate transmitter interrupt requests. transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the transmission complete interrupt enable bit, tcie, in scc2 enables the tc bit to generate transmitter interrupt requests. 13.4.2 receiver interrupts these sources can generate interrupt requests from the esci receiver: esci receiver full (scrf) ? the scrf bit in sc s1 indicates that the receive shift register has transferred a character to the s cdr. scrf can generate a receiver interrupt request. setting the esci receive interrupt enable bit, scrie, in scc2 enables the scrf bit to generate receiver interrupts. idle input (idle) ? the idle bit in scs1 indicates that 10 or 11 consecutive 1s shifted in from the rxd pin. the idle line interrupt enable bit, ilie, in scc2 enables the idle bit to generate interrupt requests. 13.4.3 error interrupts these receiver error flags in scs1 can generate interrupt requests: receiver overrun (or) ? the or bit indicates t hat the receive shift register shifted in a new character before the previous c haracter was read from the scdr. the previous character remains in the scdr, and the new character is lost. th e overrun interrupt enable bit, orie, in scc3 enables or to generate esci error interrupt requests. noise flag (nf) ? the nf bit is set when t he esci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, in scc3 enables nf to generate esci error interrupt requests. framing error (fe) ? the fe bit in scs1 is set when a 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate esci error interrupt requests. parity error (pe) ? the pe bit in scs1 is set when the esci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in scc3 enables pe to generate esci error interrupt requests. 13.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 13.5.1 wait mode the esci module remains active in wait mode. any enabled interrupt request from the esci module can bring the mcu out of wait mode. if esci module functions are not required during wait mode, reduce power consum ption by disabling the module before executing the wait instruction.
esci during break interrupts mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 121 13.5.2 stop mode the esci module is inactive in stop mode. the stop instruction does not affect esci register states. esci module operation resumes after the mcu exits stop mode. because the internal clock is i nactive during stop mode, entering stop mode during an esci transmission or reception results in invalid data. 13.6 esci during break interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see bfcr in the sim section of this data sheet . to allow software to clear status bits during a break interrupt, write a 1 to bcfe. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to bcfe. with bcfe cleared (its default state), software can read and write registers during the break stat e without affecting status bits. some status bits have a two-step read/write clearing procedure. if softw are does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is cleared.after the break, doing the second step clears the status bit. 13.7 i/o signals the esci module can share its pins wi th the general-purpose i/o pins. see figure 13-1 for the port pins that are shared. 13.7.1 esci transmit data (txd) the txd pin is the serial data output from the esc i transmitter. when the esci is enabled, the txd pin becomes an output. 13.7.2 esci receive data (rxd) the rxd pin is the serial data input to the esci re ceiver. when the esci is enabled, the rxd pin becomes an input. 13.8 registers the following registers control and monitor operation of the esci: esci control register 1, scc1 esci control register 2, scc2 esci control register 3, scc3 esci status register 1, scs1 esci status register 2, scs2 esci data register, scdr esci baud rate register, scbr esci prescaler register, scpsc esci arbiter control register, sciactl esci arbiter data register, sciadat
enhanced serial communicatio ns interface (esci) module mc68hc908qb8 data sheet, rev. 1 122 freescale semiconductor 13.8.1 esci control register 1 esci control register 1 (scc1): enables loop mode operation enables the esci controls output polarity controls character length controls esci wakeup method controls idle character detection enables parity function controls parity type loops ? loop mode select bit this read/write bit enables loop mode operation. in loop mode the rxd pin is disconnected from the esci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable esci bit this read/write bit enables the esci and the esci baud rate generator. clearing ensci sets the scte and tc bits in esci status regist er 1 and disables transmitter interrupts. 1 = esci enabled 0 = esci disabled txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. 1 = transmitter output inverted 0 = transmitter output not inverted note setting the txinv bit invert s all transmitted values including idle, break, start, and stop bits. m ? mode (character length) bit this read/write bit determines whether esci c haracters are eight or nine bits long (see table 13-4 ).the ninth bit can serve as a receiver wakeup signal or as a parity bit. 1 = 9-bit esci characters 0 = 8-bit esci characters bit 7654321bit 0 read: loops ensci txinv m wake ilty pen pty write: reset:00000000 figure 13-9. esci control register 1 (scc1)
registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 123 wake ? wakeup condition bit this read/write bit determines which condition wakes up the esci: a 1 (address mark) in the msb position of a received character or an idle condition on the rxd pin. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this read/write bit determines when the esci starts counting 1s as idle character bits. the counting begins either after the start bit or after the stop bi t. if the count begins after the start bit, then a string of 1s preceding the stop bit may cause false recognit ion of an idle character. beginning the count after the stop bit avoids false idle character recogniti on, but requires properly synchronized transmissions. 1 = idle character bit count begins after stop bit 0 = idle character bit count begins after start bit pen ? parity enable bit this read/write bit enables the esci parity function (see table 13-4 ). when enabled, the parity function inserts a parity bit in the msb position (see table 13-2 ). 1 = parity function enabled 0 = parity function disabled pty ? parity bit this read/write bit determines whether the esc i generates and checks for odd parity or even parity (see table 13-4 ). 1 = odd parity 0 = even parity note changing the pty bit in the middle of a transmission or reception can generate a parity error. 13.8.2 esci control register 2 esci control register 2 (scc2): enables these interrupt requests: ? scte bit to generate transmitter interrupt requests ? tc bit to generate transmitter interrupt requests ? scrf bit to generate receiver interrupt requests ? idle bit to generate receiver interrupt requests enables the transmitter table 13-4. character format selection control bits character format m pen:pty start bits data bits pa rity stop bits character length 0 0 x 1 8 none 1 10 bits 1 0 x 1 9 none 1 11 bits 0 1 0 1 7 even 1 10 bits 0 1 1 1 7 odd 1 10 bits 1 1 0 1 8 even 1 11 bits 1 1 1 1 8 odd 1 11 bits
enhanced serial communicatio ns interface (esci) module mc68hc908qb8 data sheet, rev. 1 124 freescale semiconductor enables the receiver enables esci wakeup transmits esci break characters sctie ? esci transmit interrupt enable bit this read/write bit enables the scte bit to generate esci transmitter interrupt requests. setting the sctie bit in scc2 enables the scte bit to generate interrupt requests. 1 = scte enabled to generate interrupt 0 = scte not enabled to generate interrupt tcie ? transmission complete interrupt enable bit this read/write bit enables the tc bit to generate esci transmitter interrupt requests. 1 = tc enabled to generate interrupt requests 0 = tc not enabled to generate interrupt requests scrie ? esci receive interrupt enable bit this read/write bit enables the scrf bit to generate esci receiver interrupt requests. setting the scrie bit in scc2 enables the scrf bit to generate interrupt requests. 1 = scrf enabled to generate interrupt 0 = scrf not enabled to generate interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to generate esci receiver interrupt requests. 1 = idle enabled to generate interrupt requests 0 = idle not enabled to generate interrupt requests te ? transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 1s from the transmit shift register to the txd pin. if softw are clears the te bit, the transmitter completes any transmission in progress before the txd returns to the idle condition (high). clearing and then setting te during a transmission queues an id le character to be sent after the character currently being transmitted. 1 = transmitter enabled 0 = transmitter disabled note writing to the te bit is not allowed when the enable esci bit (ensci) is clear. ensci is in esci control register 1. re ? receiver enable bit setting this read/write bit enables the receiver. clea ring the re bit disables the receiver but does not affect receiver interrupt flag bits. 1 = receiver enabled 0 = receiver disabled bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 13-10. esci control register 2 (scc2)
registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 125 note writing to the re bit is not allowed when the enable esci bit (ensci) is clear. ensci is in esci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines whether an idle i nput or an address mark brings the receiver out of the standby state and clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting and then clearing this read/writ e bit transmits a break character followed by a 1. the 1 after the break character guarantees recogni tion of a valid start bit. if sbk remains set, the transmitter continuously transmits break char acters with no 1s between them. 1 = transmit break characters 0 = no break characters being transmitted note do not toggle the sbk bit immediately a fter setting the scte bit. toggling sbk before the preamble begins caus es the esci to send a break character instead of a preamble. 13.8.3 esci control register 3 esci control register 3 (scc3): stores the ninth esci data bit received and the ninth esci data bit to be transmitted. enables these interrupts: ? receiver overrun ? noise error ? framing error ? parity error r8 ? received bit 8 when the esci is receiving 9-bit characters, r8 is the read-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other 8 bits. when the esci is receiving 8-bit characters, r8 is a copy of the eighth bit (bit 7). t8 ? transmitted bit 8 when the esci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift regi ster at the same time that the scdr is loaded into the transmit shift register. bit 7654321bit 0 read: r8 t8 r r orie neie feie peie write: reset:u0000000 = unimplemented r = reserved u = unaffected figure 13-11. esci control register 3 (scc3)
enhanced serial communicatio ns interface (esci) module mc68hc908qb8 data sheet, rev. 1 126 freescale semiconductor orie ? receiver overrun interrupt enable bit this read/write bit enables esci error interrupt requests generated by the receiver overrun bit, or. 1 = esci error interrupt requests from or bit enabled 0 = esci error interrupt requests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enables esci error interrupt requests generated by the noise error bit, ne. 1 = esci error interrupt requests from ne bit enabled 0 = esci error interrupt requests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enables esci error interrupt requests generated by the framing error bit, fe. 1 = esci error interrupt requests from fe bit enabled 0 = esci error interrupt requests from fe bit disabled peie ? receiver parity error interrupt enable bit this read/write bit enables esci receiver interrupt requests generated by the parity error bit, pe. 1 = esci error interrupt requests from pe bit enabled 0 = esci error interrupt requests from pe bit disabled 13.8.4 esci status register 1 esci status register 1 (scs1) contai ns flags to signal these conditions: transfer of scdr data to transmit shift register complete transmission complete transfer of receive shift register data to scdr complete receiver input idle receiver overrun noisy data framing error parity error scte ? esci transmitter empty bit this clearable, read-only bit is set when the scdr tr ansfers a character to the transmit shift register. scte can generate an esci transmitter interrupt r equest. when the sctie bit in scc2 is set, scte generates an esci transmitter interrupt request. in normal operation, clear the scte bit by reading scs1 with scte set and then writing to scdr 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented figure 13-12. esci status register 1 (scs1)
registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 127 tc ? transmission complete bit this read-only bit is set when the scte bit is se t, and no data, preamble, or break character is being transmitted. tc generates an esci transmitter interrupt request if the tcie bit in scc2 is also set. tc is cleared automatically when data, preamble, or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. 1 = no transmission in progress 0 = transmission in progress scrf ? esci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the esci data register. scrf can generate an esci receiver interrupt request. when the scrie bit in scc2 is set the scrf generates a interrupt request. in normal oper ation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive 1s appear on the receiver input. idle generates an esci receiver interrupt request if the ilie bit in scc2 is also set. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must receive a valid character that sets the scrf bit before an id le condition can set the idle bit. also, after the idle bit has been cleared, a valid character must again set the scrf bit before an idle condition can set the idle bit. 1 = receiver input idle 0 = receiver input active (or id le since the idle bit was cleared) or ? receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit ge nerates an esci error interrupt request if the orie bit in scc3 is also set. the data in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading sc s1 with or set and then reading the scdr. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an ove rrun to occur between reads of sc s1 and scdr in the flag-clearing sequence. figure 13-13 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearin g sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag-clearing sequence reads byte 3 in the scdr instead of byte 2. in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the or bit in a second read of scs1 after reading the data register. nf ? receiver noise flag bit this clearable, read-only bit is set when the esc i detects noise on the rxd pin. nf generates an nf interrupt request if the neie bit in scc3 is also set. clear the nf bit by reading scs1 and then reading the scdr. 1 = noise detected 0 = no noise detected
enhanced serial communicatio ns interface (esci) module mc68hc908qb8 data sheet, rev. 1 128 freescale semiconductor figure 13-13. flag clearing sequence fe ? receiver framing error bit this clearable, read-only bit is set when a 0 is accepted as the stop bit. fe generates an esci error interrupt request if the feie bit in scc3 also is se t. clear the fe bit by reading scs1 with fe set and then reading the scdr. 1 = framing error detected 0 = no framing error detected pe ? receiver parity error bit this clearable, read-only bit is set when the esci detects a parity error in incoming data. pe generates a pe interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. 1 = parity error detected 0 = no parity error detected byte 1 normal flag clearing sequence scrf = 1 scrf = 1 byte 2 byte 3 byte 4 scrf = 0 scrf = 1 scrf = 0 scrf = 0 byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0 read scs1 scrf = 1 or = 0 read scs1 scrf = 1 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 1 read scdr byte 2 read scdr byte 3 read scs1 scrf = 1 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 1 read scdr byte 3
registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 129 13.8.5 esci status register 2 esci status register 2 (scs2) contai ns flags to signal these conditions: break character detected reception in progress bkf ? break flag bit this clearable, read-only bit is set when the esci detects a break character on the rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a interrupt request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become set again only after 1s again appear on the rxd pin followed by another break character. 1 = break character detected 0 = no break character detected rpf ? reception in progress flag bit this read-only bit is set when the receiver detects a 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character. polling rpf before disabling the esci module or entering stop mode can show whethe r a reception is in progress. 1 = reception in progress 0 = no reception in progress 13.8.6 esci data register the esci data register (scdr) is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the esci data register. r7/t7:r0/t0 ? receive/transmit data bits reading scdr accesses the read- only received data bits, r7:r0. writing to scdr writes the data to be transmitted, t7:t0. note do not use read-modify-write instructions on the esci data register. bit 7654321bit 0 read:000000bkfrpf write: reset:00000000 = unimplemented figure 13-14. esci status register 2 (scs2) bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 13-15. esci data register (scdr)
enhanced serial communicatio ns interface (esci) module mc68hc908qb8 data sheet, rev. 1 130 freescale semiconductor 13.8.7 esci baud rate register the esci baud rate register (scbr) together with the esci prescaler register selects the baud rate for both the receiver and the transmitter. note there are two prescalers available to adjust the baud rate ? one in the esci baud rate register and one in the esci prescaler register. lint ? lin transmit enable this read/write bit selects the enhanced esci features for the local interconnect network (lin) protocol as shown in table 13-5 . linr ? lin receiver bits this read/write bit selects the enhanced esci features for the local interconnect network (lin) protocol as shown in table 13-5 . in lin (version 1.2 and later) systems, the master node transmits a break character which will appear as 11.05?14.95 dominant bits to the slave node. a dat a character of 0x00 sent from the master might appear as 7.65?10.35 dominant bit times. this is due to the oscillator tolerance requirement that the slave node must be within 15% of the master node's oscillator. because a slave node cannot know if it is running faster or slower than the master node (prior to synchronization), the linr bit allows the slave node to differentiate between a 0x00 character of 10.35 bits and a break character of 11.05 bits. the break symbol length must be verified in software in any case, but the linr bit serves as a filter, preventing false detections of break characte rs that are really 0x00 data characters. bit 7654321bit 0 read: lint linr scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 r = reserved figure 13-16. esci baud rate register (scbr) table 13-5. esci lin control bits lint linr m functionality 0 0 x normal esci functionality 0 1 0 11-bit break detect enabled for lin receiver 0 1 1 12-bit break detect enabled for lin receiver 1 0 0 11-bit generation enabled for lin transmitter 1 0 1 12-bit generation enabled for lin transmitter 1 1 0 11-bit break detect/11-bit generation enabled for lin 1 1 1 12-bit break detect/12-bit generation enabled for lin
registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 131 scp1 and scp0 ? esci baud rate register prescaler bits these read/write bits select the baud rate register prescaler divisor as shown in table 13-6 . scr2?scr0 ? esci baud rate select bits these read/write bits select the esci baud rate divisor as shown in table 13-7 . reset clears scr2?scr0. 13.8.8 esci prescaler register the esci prescaler register (scpsc) together with the esci baud rate register selects the baud rate for both the receiver and the transmitter. note there are two prescalers available to adjust the baud rate ? one in the esci baud rate register and one in the esci prescaler register. table 13-6. esci baud rate prescaling scp[1:0] baud rate register prescaler divisor (bpd) 00 1 01 3 10 4 11 13 table 13-7. esci baud rate selection scr[2:1:0] baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 bit 7654321bit 0 read: pds2 pds1 pds0 pssb4 pssb3 pssb2 pssb1 pssb0 write: reset:00000000 figure 13-17. esci prescaler register (scpsc)
enhanced serial communicatio ns interface (esci) module mc68hc908qb8 data sheet, rev. 1 132 freescale semiconductor pds2?pds0 ? prescaler divisor select bits these read/write bits select the prescaler divisor as shown in table 13-8 . note the setting of ?000? will bypass not only this prescaler but also the prescaler divisor fine adjust (pdfa). it is not recommended to bypass the prescaler while ensci is set, because the switching is not glitch free. pssb4?pssb0 ? clock insertion select bits these read/write bits select the number of clocks inserted in each 32 output cycle frame to achieve more timing resolution on the average prescaler frequency as shown in table 13-9 . table 13-8. esci prescaler division ratio pds[2:1:0] prescaler divisor (pd) 0 0 0 bypass this prescaler 001 2 010 3 011 4 100 5 101 6 110 7 111 8 table 13-9. esci prescaler divisor fine adjust pssb[4:3:2:1:0] prescaler di visor fine adjust (pdfa) 00000 0/32 = 0 00001 1/32 = 0.03125 00010 2/32 = 0.0625 00011 3/32 = 0.09375 0 0 1 0 0 4/32 = 0.125 00101 5/32 = 0.15625 00110 6/32 = 0.1875 00111 7/32 = 0.21875 0 1 0 0 0 8/32 = 0.25 01001 9/32 = 0.28125 0 1 0 1 0 10/32 = 0.3125 0 1 0 1 1 11/32 = 0.34375 0 1 1 0 0 12/32 = 0.375 0 1 1 0 1 13/32 = 0.40625 0 1 1 1 0 14/32 = 0.4375 continued on next page
registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 133 use the following formula to calculate the esci baud rate: where: sci clock source = bus clock or cgmxclk (selecte d by scibdsrc in the configuration register) bpd = baud rate register prescaler divisor bd = baud rate divisor pd = prescaler divisor pdfa = prescaler divisor fine adjust table 13-10 shows the esci baud rates that can be generated with a 4.9152-mhz bus frequency. 0 1 1 1 1 15/32 = 0.46875 10000 16/32 = 0.5 1 0 0 0 1 17/32 = 0.53125 1 0 0 1 0 18/32 = 0.5625 1 0 0 1 1 19/32 = 0.59375 1 0 1 0 0 20/32 = 0.625 1 0 1 0 1 21/32 = 0.65625 1 0 1 1 0 22/32 = 0.6875 1 0 1 1 1 23/32 = 0.71875 1 1 0 0 0 24/32 = 0.75 1 1 0 0 1 25/32 = 0.78125 1 1 0 1 0 26/32 = 0.8125 1 1 0 1 1 27/32 = 0.84375 1 1 1 0 0 28/32 = 0.875 1 1 1 0 1 29/32 = 0.90625 1 1 1 1 0 30/32 = 0.9375 1 1 1 1 1 31/32 = 0.96875 table 13-9. esci prescaler divisor fine adjust (continued) pssb[4:3:2:1:0] prescaler di visor fine adjust (pdfa) frequency of the sci clock source 64 x bpd x bd x (pd + pdfa) baud rate =
enhanced serial communicatio ns interface (esci) module mc68hc908qb8 data sheet, rev. 1 134 freescale semiconductor table 13-10. esci baud rate selection examples pds[2:1:0] pssb[4:3:2:1:0] scp[1:0] prescaler divisor (bpd) scr[2:1:0] baud rate divisor (bd) baud rate (f bus = 4.9152 mhz) 000 xxxxx 00 1 000 1 76,800 111 00000 00 1 000 1 9600 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 9562.65 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 9525.58 1 1 1 1 1 1 1 1 0 0 1 0 0 0 1 8563.07 000 xxxxx 00 1 001 2 38,400 000 xxxxx 00 1 010 4 19,200 000 xxxxx 00 1 011 8 9600 000 xxxxx 00 1 100 16 4800 000 xxxxx 00 1 101 32 2400 000 xxxxx 00 1 110 64 1200 000 xxxxx 00 1 111 128 600 000 xxxxx 01 3 000 1 25,600 000 xxxxx 01 3 001 2 12,800 000 xxxxx 01 3 010 4 6400 000 xxxxx 01 3 011 8 3200 000 xxxxx 01 3 100 16 1600 000 xxxxx 01 3 101 32 800 000 xxxxx 01 3 110 64 400 000 xxxxx 01 3 111 128 200 000 xxxxx 10 4 000 1 19,200 000 xxxxx 10 4 001 2 9600 000 xxxxx 10 4 010 4 4800 000 xxxxx 10 4 011 8 2400 000 xxxxx 10 4 100 16 1200 000 xxxxx 10 4 101 32 600 000 xxxxx 10 4 110 64 300 000 xxxxx 10 4 111 128 150 000 xxxxx 11 13 000 1 5908 000 xxxxx 11 13 001 2 2954 000 xxxxx 11 13 010 4 1477 000 xxxxx 11 13 011 8 739 000 xxxxx 11 13 100 16 369 000 xxxxx 11 13 101 32 185 000 xxxxx 11 13 110 64 92 000 xxxxx 11 13 111 128 46
esci arbiter mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 135 13.9 esci arbiter the esci module comprises an arbiter module designed to support software for communication tasks as bus arbitration, baud rate recovery and break time det ection. the arbiter module consists of an 9-bit counter with 1-bit overflow and control logic. the c an control operation mode via the esci arbiter control register (sciactl). 13.9.1 esci arbite r control register am1 and am0 ? arbiter mode select bits these read/write bits select the mode of the arbiter module as shown in table 13-11 . alost ? arbitration lost flag this read-only bit indicates loss of arbitr ation. clear alost by writing a 0 to am1. aclk ? arbiter counter clock select bit this read/write bit selects the arbiter counter clock source. 1 = arbiter counter is clocked with one half of t he esci input clock generated by the esci prescaler 0 = arbiter counter is clocked wi th the bus clock divided by four note for aclk = 1, the arbiter input clock is driven from the esci prescaler. the prescaler can be clocked by either the bus clock or cgmxclk depending on the state of the scibdsrc bit in configuration register. afin? arbiter bit time measurement finish flag this read-only bit indicates bit ti me measurement has finished. clea r afin by writing any value to sciactl. 1 = bit time measurement has finished 0 = bit time measurement not yet finished bit 7654321bit 0 read: am1 alost am0 aclk afin arun arovfl ard8 write: reset:00000000 = unimplemented figure 13-18. esci arbiter control register (sciactl) table 13-11. esci arbiter selectable modes am[1:0] esci arbiter mode 0 0 idle / counter reset 0 1 bit time measurement 1 0 bus arbitration 1 1 reserved / do not use
enhanced serial communicatio ns interface (esci) module mc68hc908qb8 data sheet, rev. 1 136 freescale semiconductor arun? arbiter counter running flag this read-only bit indicates the arbiter counter is running. 1 = arbiter counter running 0 = arbiter counter stopped arovfl? arbiter counter overflow bit this read-only bit indicates an arbiter counter ov erflow. clear arovfl by writing any value to sciactl. writing 0s to am1 and am0 resets the counter keeps it in this idle state. 1 = arbiter counter overflow has occurred 0 = no arbiter counter overflow has occurred ard8? arbiter counter msb this read-only bit is the msb of the 9-bit arbiter co unter. clear ard8 by writing any value to sciactl. 13.9.2 esci arbite r data register ard7?ard0 ? arbiter least significant counter bits these read-only bits are the eight lsbs of the 9-bi t arbiter counter. clear ard7?ard0 by writing any value to sciactl. writing 0s to am1 and am0 permanent ly resets the counter and keeps it in this idle state. 13.9.3 bit time measurement two bit time measurement modes, described here, are available acco rding to the state of aclk. 1. aclk = 0 ? the counter is clocked with one half of the bus clock. the counter is started when a falling edge on the rxd pin is detected. the c ounter will be stopped on the next falling edge. arun is set while the counter is running, afin is se t on the second falling edge on rxd (for instance, the counter is stopped). this mode is used to recover the received baud rate. see figure 13-20 . 2. aclk = 1 ? the counter is clocked with one hal f of the esci input clock generated by the esci prescaler. the counter is started when a 0 is detected on rxd (see figure 13-21 ). a 0 on rxd on enabling the bit time measurement with aclk = 1 leads to immediate start of the counter (see figure 13-22 ). the counter will be stopped on the next rising edge of rxd. this mode is used to measure the length of a received break. bit 7654321bit 0 read: ard7 ard6 ard5 ard4 ard3 ard2 ard1 ard0 write: reset:00000000 = unimplemented figure 13-19. esci arbiter data register (sciadat)
esci arbiter mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 137 figure 13-20. bit time measurement with aclk = 0 figure 13-21. bit time measurement with aclk = 1, scenario a figure 13-22. bit time measurement with aclk = 1, scenario b write sciactl counter starts, counter stops, measured time read result rxd with $20 arun = 1 afin = 1 out of sciadat write sciactl with $30 counter starts, arun = 1 counter stops, afin = 1 measured time read result rxd out of sciadat write sciactl counter starts, counter stops, measured time read result rxd out of sciadat afin = 1 arun = 1 with $30
enhanced serial communicatio ns interface (esci) module mc68hc908qb8 data sheet, rev. 1 138 freescale semiconductor 13.9.4 arbitration mode if am[1:0] is set to 10, the arbiter module operates in arbitration mode. on every rising edge of sci_txd (output of the transmit shift register, see figure 13-2 ), the counter is started. when the counter reaches $38 (aclk = 0) or $08 (aclk = 1), rxd is statically sensed. if in this case, rxd is sensed low (for example, another bus is driving the bus dominant) alos t is set. as long as alost is set, the txd pin is forced to 1, resulting in a seized transmission. if sci_txd senses 0 without having sensed a 0 befor e on rxd, the counter will be reset, arbitration operation will be restarted after the next rising edge of sci_txd.
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 139 chapter 14 system integration module (sim) 14.1 introduction this section describes the system integration module (sim), which supports up to 24 external and/or internal interrupts. together with the central processo r unit (cpu), the sim controls all microcontroller unit (mcu) activities. a block diagr am of the sim is shown in figure 14-1 . the sim is a system state controller that coordinates cpu and exception timing. the sim is responsible for: bus clock generation and control for cpu and peripherals ? stop/wait/reset/break entry and recovery ? internal clock control master reset control, including power-on reset (por) and computer operating properly (cop) timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing 14.2 rst and irq pins initialization rst and irq pins come out of reset as pta3 and pta2 respectively. rst and irq functions can be activated by programing config2 accordingly. refer to chapter 5 configuration register (config) . table 14-1. signal name conventions signal name description busclkx4 buffered clock from the internal, rc or xtal oscillator circuit. busclkx2 the busclkx4 frequency divided by two. this signal is again divided by two in the sim to generate the internal bus clocks (bus clock = busclkx4 4). address bus internal address bus data bus internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal
system integration module (sim) mc68hc908qb8 data sheet, rev. 1 140 freescale semiconductor figure 14-1. sim block diagram 14.3 sim bus clock control and generation the bus clock generator provides system clock signa ls for the cpu and peripherals on the mcu. the system clocks are generated from an incoming clock, busclkx2, as shown in figure 14-2 . figure 14-2. sim clock signals stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to oscillator) busclkx2 (from oscillator) internal clocks master reset control reset pin logic illegal opcode (from cpu) illegal address (from address map decoders) cop timeout (from cop module) interrupt sources cpu interface reset control sim counter cop clock busclkx4 (from oscillator) 2 lvi reset (from lvi module) v dd internal pull-up forced mon mode entry (from menrst module) 2 bus clock generators sim sim counter from oscillator from oscillator busclkx2 busclkx4
reset and system initialization mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 141 14.3.1 bus timing in user mode , the internal bus frequency is the oscillat or frequency (busclkx4) divided by four. 14.3.2 clock star t-up from por when the power-on reset module generates a reset, th e clocks to the cpu and peripherals are inactive and held in an inactive phase until after the 4096 busclkx4 cycle por time out has completed. the ibus clocks start upon completion of the time out. 14.3.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt or reset, the sim allows busclkx4 to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay time out. this time out is selectable as 4096 or 32 busclkx4 cycles. see 14.7.2 stop mode . in wait mode, the cpu clocks are inactive. the sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to s ee if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. 14.4 reset and s ystem initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly module (cop) low-voltage inhibit module (lvi) illegal opcode illegal address all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all register s to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 14.5 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr). see 14.8 sim registers . 14.4.1 external pin reset the rst pin circuits include an internal pul lup device. pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for at least the minimum t rl time. figure 14-3 shows the relative timing. the rst pin function is only available if the rsten bit is set in the config2 register. figure 14-3. external reset timing rst address bus pc vect h vect l busclkx2
system integration module (sim) mc68hc908qb8 data sheet, rev. 1 142 freescale semiconductor 14.4.2 active resets from internal sources the rst pin is initially setup as a general-purpose i nput after a por. setting the rsten bit in the config2 register enables the pin for the reset functi on. this section assumes the rsten bit is set when describing activity on the rst pin. note for por and lvi resets, the sim cycles through 4096 busclkx4 cycles. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 14-4 . the cop reset is asynchronous to the bus clock. the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. all internal reset sources actively pull the rst pin low for 32 busclkx4 cycles to allow resetting of external peripherals. the internal reset signal irst continues to be asserted for an additional 32 cycles (see figure 14-4 ). an internal reset can be caused by an ille gal address, illegal opcode, cop time out, lvi, or por (see figure 14-5 ). figure 14-4. internal reset timing figure 14-5. sources of internal reset table 14-2. reset recovery timing reset recovery type actual number of cycles por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) irst rst rst pulled low by mcu address 32 cycles 32 cycles vector high busclkx4 bus illegal address rst illegal opcode rst coprst por lvi internal reset
reset and system initialization mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 143 14.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power on has occurred. the sim counter counts out 4096 busclkx4 cycles. sixty-four busclkx4 cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power on, the following events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables the oscillator to drive busclkx4. internal clocks to the cpu and modules are hel d inactive for 4096 busclkx4 cycles to allow stabilization of the oscillator. the por bit of the sim reset status register (srsr) is set. see figure 14-6 . figure 14-6. por recovery 14.4.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of th e cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all internal reset sources. to prevent a cop module time out, write any val ue to location $ffff. writing to location $ffff clears the cop counter and stages 12?5 of the sim counter. the sim counter output, which occurs at least every (2 12 ? 2 4 ) busclkx4 cycles, drives the cop counte r. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first time out. the cop module is disabled during a break interrupt with monitor mode when bdcop bit is set in break auxiliary register (brkar). 14.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. porrst osc1 busclkx4 busclkx2 rst address bus 4096 cycles 32 cycles 32 cycles $fffe $ffff (rst pin is a general-purpose input after a por)
system integration module (sim) mc68hc908qb8 data sheet, rev. 1 144 freescale semiconductor if the stop enable bit, stop, in the mask option register is 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode re set. the sim actively pulls down the rst pin for all internal reset sources. 14.4.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped add ress does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. see figure 2-1. memory map for memory ranges. 14.4.2.5 low-voltage inhibit (lvi) reset the lvi asserts its output to the sim when the v dd voltage falls to the lvi trip voltage v tripf . the lvi bit in the sim reset status register (srsr) is set, and the external reset pin (rst ) is held low while the sim counter counts out 4096 busclkx4 cycles after v dd rises above v tripr . sixty-four busclkx4 cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. the sim actively pulls down the (rst ) pin for all internal reset sources. 14.5 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly module (cop). the sim counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of sim counters and supplies the clock for the cop module. the sim counter is clocked by the falling edge of busclkx4. 14.5.1 sim counter du ring power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initializ ed, it enables the oscillator to drive the bus clock state machine. 14.5.2 sim counter du ring stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the configuration register 1 (config1). if the ssrec bit is a 1, then the stop recovery is reduced from the normal delay of 4096 busclkx4 cycles down to 32 busclkx4 cycles. this is ideal for applications using canned oscillators that do not require long st art-up times from stop mode. external crystal applications should use the full stop recovery time, that is, wi th ssrec cleared in the configuration register 1 (config1). 14.5.3 sim counter and reset states external reset has no effect on the sim counter (see 14.7.2 stop mode for details.) the sim counter is free-running after all reset states. see 14.4.2 active resets from internal sources for counter control and internal reset recovery sequences.
exception control mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 145 14.6 exception control normal sequential program execution can be changed in three different ways: 1. interrupts a. maskable hardware cpu interrupts b. non-maskable software interrupt instruction (swi) 2. reset 3. break interrupts 14.6.1 interrupts an interrupt temporarily changes the sequence of pr ogram execution to respond to a particular event. figure 14-7 flow charts the handling of system interrupts. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the i bit is cleared). at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 14-8 shows interrupt entry timing. figure 14-9 shows interrupt recovery timing. 14.6.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 14-10 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. the lda opcode is prefetched by both the int1 and int2 return-from-interrupt (rti) instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note to maintain compatibility with the m6805 family , the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine.
system integration module (sim) mc68hc908qb8 data sheet, rev. 1 146 freescale semiconductor figure 14-7. interrupt processing no no no yes no no yes no yes yes (as many interrupts as exist on chip) i bit set? from reset break interrupt? i bit set? irq interrupt? timer interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers execute instruction yes yes stack cpu registers set i bit load pc with interrupt vector
exception control mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 147 figure 14-8 . interrupt entry figure 14-9. interrupt recovery figure 14-10 . interrupt recognition example module data bus r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr address bus dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module data bus r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 address bus ccr a x pc ? 1[7:0] pc ? 1[15:8] opcode operand i bit cli lda int1 pulh rti int2 background routine #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine
system integration module (sim) mc68hc908qb8 data sheet, rev. 1 148 freescale semiconductor 14.6.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 14.6.2 interrupt status registers the flags in the interrupt status registers identify maskable interrupt sources. table 14-3 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. table 14-3. interrupt sources priority source flag mask (1) 1. the i bit in the condition code register is a global mask for all interrupt sources except the swi instruction. int register flag vector address highest lowest reset ? ? ? $fffe?$ffff swi instruction ? ? ? $fffc?$fffd irq pin irqf imask if1 $fffa?$fffb timer channel 0 interrupt ch0f ch0ie if3 $fff6?$fff7 timer channel 1 interrupt ch1f ch1ie if4 $fff4?$fff5 timer overflow interrupt tof toie if5 $fff2?$fff3 tim channel 2 vector ch2f ch2ie if6 $fff0?$fff1 tim channel 3 vector ch3f ch3ie if7 $ffee?$ffef esci error vector or, hf, fe, pe orie, neie, feie, peie if9 $ffea?$ffeb esci receive vector scrf scrie if10 $ffe8?$ffe9 esci transmit vector scte, tc sctie, tcie if11 $ffe6?$ffe7 spi receive sprf, ovrf, modf sprie, errie if12 $ffe4?$ffe5 spi transmit spte sptie if13 $ffe2?$ffe3 keyboard interrupt keyf imaskk if14 $ffe0?$ffe1 adc conversion complete interrupt coco aien if15 $ffde?$ffdf
exception control mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 149 14.6.2.1 interrupt status register 1 if1 and if3?if6 ? interrupt flags these flags indicate the presence of interrupt requests from the sources shown in table 14-3 . 1 = interrupt request present 0 = no interrupt request present bit 0, 1, and 3? always read 0 14.6.2.2 interrupt status register 2 if7?i f 14 ? interrupt flags this flag indicates the presence of interr upt requests from the sources shown in table 14-3 . 1 = interrupt request present 0 = no interrupt request present 14.6.2.3 interrupt status register 3 if15?i f 22 ? interrupt flags these flags indicate the presence of interrupt requests from the sources shown in table 14-3 . 1 = interrupt request present 0 = no interrupt request present bit 7654321bit 0 read: if6 if5 if4 if3 0 if1 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 14-11. interrupt status register 1 (int1) bit 7654321bit 0 read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 r= reserved figure 14-12. interrupt status register 2 (int2) bit 7654321bit 0 read: if22 if21 if20 if19 if18 if17 if16 if15 write:rrrrrrrr reset:00000000 r= reserved figure 14-13. interrupt status register 3 (int3)
system integration module (sim) mc68hc908qb8 data sheet, rev. 1 150 freescale semiconductor 14.6.3 reset all reset sources always have equal and highest priority and cannot be arbitrated. 14.6.4 break interrupts the break module can stop normal program flow at a software programmable break point by asserting its break interrupt output. (see chapter 17 development support .) the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 14.6.5 status flag pr otection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select whether flags are protected from bei ng cleared by properly initializing the break clear flag enable bit (bcfe) in the break flag control register (bfcr). protecting flags in break mode ensures that set fl ags will not be cleared while in break mode. this protection allows registers to be freely read and writ ten during break mode without losing status flag information. setting the bcfe bit enables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 14.7 low-power modes executing the wait or stop instruction puts the mcu in a low power- consumption mode for standby situations. the sim holds the cpu in a non-clocked st ate. the operation of each of these modes is described below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 14.7.1 wait mode in wait mode, the cpu clocks are inactive while the peripheral clocks continue to run. figure 14-14 shows the timing for wait mode entry. figure 14-14. wait mode entry timing a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wa it instruction during which the interrupt occurred. wait addr + 1 same same address bus data bus previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction.
low-power modes mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 151 in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset (or break in emulation mode). a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the break status register (bsr). if the cop disable bit, copd, in the configuration register is 0, then the comp uter operating properly module (cop) is enabled and remains active in wait mode. figure 14-15 and figure 14-16 show the timing for wait recovery. figure 14-15. wait recovery from interrupt figure 14-16. wait recovery from internal reset 14.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset or break also causes an exit from stop mode. the sim disables the oscillator signals (busclkx2 and busclkx4) in stop mode, stopping the cpu and peripherals. if osceninstop is set, busclkx4 will remain running in stop and can be used to run the awu. stop recovery time is selectable using the ssrec bit in the configuration register 1 (config1). if ssrec is set, stop recovery is reduced from the normal delay of 4096 busclkx4 cycles down to 32. this is ideal for the internal oscillator , rc oscillator, and external oscillator options which do not require long start-up times from stop mode. note external crystal applications should use the full stop recovery time by clearing the ssrec bit. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 address bus data bus exitstopwait note: exitstopwait = rst pin or cpu interrupt address bus data bus rst (1) $a6 $a6 $6e0b rst vct h rst vct l $a6 busclkx4 32 cycles 32 cycles 1. rst is only available if the rsten bit in the config2 register is set.
system integration module (sim) mc68hc908qb8 data sheet, rev. 1 152 freescale semiconductor the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 14-17 shows stop mode entry timing and figure 14-18 shows the stop mode recovery time from interrupt or break note to minimize stop current, all pins conf igured as inputs should be driven to a logic 1 or logic 0. figure 14-17. stop mode entry timing figure 14-18. stop mode recovery from interrupt 14.8 sim registers the sim has two memory mapped registers. 14.8.1 sim reset status register the srsr register contains flags that show the s ource of the last reset. the status register will automatically clear after reading srsr. a power-on rese t sets the por bit and clears all other bits in the register. all other reset sources set the individual fl ag bits but do not clear the register. more than one reset source can be flagged at any time depending on the c onditions at the time of the internal or external reset. for example, the por and lvi bit can both be set if the power supply has a slow rise time. bit 7654321bit 0 read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 = unimplemented figure 14-19. sim reset status register (srsr) stop addr + 1 same same address bus data bus previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. busclkx4 interrupt address bus stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period
sim registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 153 por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit (illegal attempt to fetch an opcode from an unimplemented address) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr modrst ? monitor mode entry module reset bit 1 = last reset caused by monitor mode entry when vector locations $fffe and $ffff are $ff after por while irq v tst 0 = por or read of srsr lvi ? low voltage inhibit reset bit 1 = last reset caused by lvi circuit 0 = por or read of srsr 14.8.2 break flag control register the break control register (bfcr) contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r = reserved figure 14-20. break flag control register (bfcr)
system integration module (sim) mc68hc908qb8 data sheet, rev. 1 154 freescale semiconductor
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 155 chapter 15 serial peripheral interface (spi) module 15.1 introduction this section describes the serial peripheral interfac e (spi) module, which allows full-duplex, synchronous, serial communications with peripheral devices. the spi shares its pins with general-purpose input/output (i/o) port pins. see figure 15-1 for port location of these shared pins. 15.2 features features of the spi module include: full-duplex operation master and slave modes double-buffered operation with separate transmit and receive registers four master mode frequencies (maximum = bus frequency 2) maximum slave mode frequency = bus frequency serial clock with programmable polarity and phase two separately enabled interrupts: ? sprf (spi receiver full) ? spte (spi transmitter empty) mode fault error flag with interrupt capability overflow error flag with interrupt capability programmable wired-or mode
serial peripheral in terface (spi) module mc68hc908qb8 data sheet, rev. 1 156 freescale semiconductor figure 15-1. block diagram highlighting spi block and pins rst , irq : pins have internal pull up device all port pins have prog rammable pull up device pta[0:5]: higher current sink and source capability pta0/tch0/ad0/kbi0 pta1/tch1/ad1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 4-channel 16-bit timer module keyboard interrupt module external interrupt module auto wakeup low-voltage inhibit cop module 10-channel 10-bit adc enhanced serial ptb0/sck/ad4 ptb ddrb m68hc08 cpu pta ddra ptb1/mosi/ad5 ptb2/miso/ad6 ptb3/ss /ad7 ptb4/rxd/ad8 ptb5/txd/ad9 ptb6/tch2 ptb7/tch3 power supply v dd v ss clock generator communications interface module module serial peripheral interface mc68hc908qb8 8192 bytes user flash 256 bytes user ram mc68hc908qb8 monitor rom break module development support
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 157 15.3 functional description the spi module allows full-dupl ex, synchronous, serial communica tion between the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi operation can be interrupt driven. the following paragraphs describe the operation of the spi module. figure 15-2. spi module block diagram transmitter interrupt request receiver/error interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 clock select 2 clock divider 8 32 128 clock logic cpha cpol spi sprie spe spwom sprf spte ovrf m s pin control logic receive data register sptie spe internal bus busclk modfen errie control modf spmstr mosi miso spsck ss
serial peripheral in terface (spi) module mc68hc908qb8 data sheet, rev. 1 158 freescale semiconductor 15.3.1 master mode the spi operates in master mode when the spi master bit, spmstr, is set. note in a multi-spi system, configure the spi modules as master or slave before enabling them. enable the master spi before enabling the slave spi. disable the slave spi before disabling the master spi. see 15.8.1 spi control register . only a master spi module can initiate transmissions. software begins the transmission from a master spi module by writing to the transmit data register. if the sh ift register is empty, the byte immediately transfers to the shift register, setting the spi transmitter empty bit, spte. the byte begins shifting out on the mosi pin under the control of the serial clock. see figure 15-3 . figure 15-3. full-duplex master-slave connections the spr1 and spr0 bits control the baud rate generator and determine the speed of the shift register. (see 15.8.2 spi status and control register .) through the spsck pin, the baud rate generator of the master also controls the shift register of the slave peripheral. while the byte shifts out on the mosi pin of the master, another byte shifts in from the slave on the master?s miso pin. the transmission ends when the receiver full bit, sprf, becomes set. at the same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, sprf signals the end of a transmission. software clears spr f by reading the spi status and control register (spscr) with sprf set and then reading the spi data register (spdr). writing to spdr clears spte. 15.3.2 slave mode the spi operates in slave mode when spmstr is clear . in slave mode, the spsck pin is the input for the serial clock from the master mcu. before a data transmission occurs, the ss pin of the slave spi must be low. ss must remain low until the transmission is complete. see 15.3.6.2 mode fault error . in a slave spi module, data enters the shift register und er the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it transfers to the receive data register, and the sprf bit is set. to prevent an overflow condit ion, slave software then must read the receive data register before another full byte enters the shift register. the maximum frequency of the spsck fo r an spi configured as a slave is the bus clock speed (which is twice as fast as the fastest master spsck clock t hat can be generated). th e frequency of the spsck for an spi configured as a slave does not have to correspond to any spi baud rate. the baud rate only shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 159 controls the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. when the master spi starts a transmission, the data in the slave shift register begins shifting out on the miso pin. the slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. the slave must write to its tr ansmit data register at l east one bus cycle before the master starts the next transmission. otherwise, the byte already in the slave shift register shifts out on the miso pin. data written to the slave shift register during a transmission remains in a buffer until the end of the transmission. when the clock phase bit (cpha) is set, the first e dge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. see 15.3.3 transmission formats . note spsck must be in the proper idle state before the slave is enabled to prevent spsck from appearing as a clock edge. 15.3.3 transmission formats during an spi transmission, data is simultaneously tr ansmitted (shifted out serially) and received (shifted in serially). a serial clock synchronizes shifting and sampling on the two serial data lines. a slave select line allows selection of an individual slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the slave select line can optionally be used to indicate multiple-master bus contention. 15.3.3.1 clock phase and polarity controls software can select any of four combinations of se rial clock (spsck) phase a nd polarity using two bits in the spi control register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no signi ficant effect on the transmission format. the clock phase (cpha) control bit selects one of tw o fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with periphera l slaves having different requirements. note before writing to the cpol bit or the cpha bit, disable the spi by clearing the spi enable bit (spe). 15.3.3.2 transmission format when cpha = 0 figure 15-4 shows an spi transmission in which cpha = 0. the figure should not be used as a replacement for data sheet parametric information. when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. after the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the falling edge of ss . any data written after the falling edge is stored in th e transmit data register and transferred to the shift register after the current transmission.
serial peripheral in terface (spi) module mc68hc908qb8 data sheet, rev. 1 160 freescale semiconductor figure 15-4. transmission format (cpha = 0) two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slav e timing diagram because the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are di rectly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is low, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. (see 15.3.6.2 mode fault error .) when cpha = 0, the first spsck edge is the msb capture strobe. therefore, the slave must begin driving its data before the first spsck edge, and a falling edge on the ss pin is used to start the slave data transmission. the slave?s ss pin must be toggled back to high and then low again between each byte tr ansmitted as shown in figure 15-5 . figure 15-5. cpha/ss timing 15.3.3.3 transmission format when cpha = 1 figure 15-6 shows an spi transmission in which cpha = 1. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram because the serial clock (spsck), master in/s lave out (miso), and master out/slave in (mosi) pins are directly connected between the master and t he slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is low, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconf igured as general-purpose i/o not affecting the spi. (see 15.3.6.2 mode fault error .) when cpha = 1, the master begins driv ing its mosi pin on the first spsck edge. therefore, the slave uses the first sps ck edge as a start transmission signal. the ss pin can bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck; cpol = 0 spsck; cpol =1 mosi from master miso from slave ss ; to slave capture strobe byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 161 remain low between transmissions. this format may be preferable in systems having only one master and only one slave driving the miso data line. figure 15-6. transmission format (cpha = 1) when cpha = 1 for a slave, the first edge of the spsck indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. after the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the first edge of spsck. any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission. 15.3.3.4 transmission initiation latency when the spi is configured as a master (spmstr = 1), writing to the spdr st arts a transmission. cpha has no effect on the delay to the start of the transmiss ion, but it does affect the initial state of the spsck signal. when cpha = 0, the spsck signal remains inactive for the first half of the first spsck cycle. when cpha = 1, the first spsck cycl e begins with an edge on the spsck line from its inactive to its active level. the spi clock rate (selected by spr1 :spr0) affects the delay from the write to spdr and the start of the spi transmission. (see figure 15-7 .) the internal spi clock in the master is a free-running derivative of the internal mcu clock. to conserve power, it is enabled only when both the spe and spmstr bits are set. because the spi clock is free-running, it is uncertain where the write to the spdr occurs relative to the slower spsck. this uncertainty causes the variation in the initiation delay shown in figure 15-7 . this delay is no longer than a single spi bi t time. that is, the maximum delay is two mcu bus cycles for div2, eight mcu bus cycles for di v8, 32 mcu bus cycles for div32, and 128 mcu bus cycles for div128. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck; cpol = 0 spsck; cpol =1 mosi from master miso from slave ss ; to slave capture strobe
serial peripheral in terface (spi) module mc68hc908qb8 data sheet, rev. 1 162 freescale semiconductor figure 15-7. transmission start delay (master) write to spdr initiation delay bus mosi spsck cpha = 1 spsck cpha = 0 spsck cycle number msb bit 6 12 clock write to spdr earliest latest spsck = bus clock 2; earliest latest 2 possible start points spsck = bus clock 8; 8 possible start points earliest latest spsck = bus clock 32; 32 possible start points earliest latest spsck = bus clock 128; 128 possible start points write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock initiation delay from write spdr to transfer begin
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 163 15.3.4 queuing transmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transm itted immediately after the previous transmission has completed. the spi transmitter empty flag (spte) indicates when the transmit data buffer is ready to accept new data. write to the transmit da ta register only when the spte bit is high. figure 15-8 shows the timing associated wi th doing back-to-back transmissi ons with the spi (spsck has cpha: cpol = 1:0). figure 15-8. sprf/spte interrupt timing the transmit data buffer allows back- to-back transmissions without the sl ave precisely timing its writes between transmissions as in a system with a single data buffer. also, if no new data is written to the data buffer, the last value contained in the shift r egister is the next data word to be transmitted. for an idle master or idle slave that has no data loaded into its transmit buffer, the spte is set again no more than two bus cycles after the transmit buffer emptie s into the shift register. this allows the user to queue up a 16-bit value to send. for an already active sl ave, the load of the shift register cannot occur until the transmission is completed. this implies that a back-to-back write to the transmit data register is not possible. spte indicates when the next write can occur. bit 3 mosi spsck spte write to spdr 1 write byte 2 to spdr, queueing byte 2 write byte 1 to spdr, clearing spte bit. byte 1 transfers from transmit data 3 1 2 2 3 5 register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data write byte 3 to spdr, queueing byte byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 read spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 read spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 read spdr, clearing sprf bit. 11 read spscr with sprf bit set. cpha:cpol = 1:0
serial peripheral in terface (spi) module mc68hc908qb8 data sheet, rev. 1 164 freescale semiconductor 15.3.5 resetting the spi any system reset completely resets the spi. partial resets occur whenever the spi enable bit (spe) is 0. whenever spe is 0, the following occurs: the spte flag is set. any transmission currently in progress is aborted. the shift register is cleared. the spi state counter is cleared, making it ready for a new complete transmission. all the spi pins revert back to being general-purpose i/o. these items are reset only by a system reset: all control bits in the spcr register all control bits in the spscr regist er (modfen, errie, spr1, and spr0) the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe betw een transmissions without having to set all control bits again w hen spe is set high fo r the next transmission. by not resetting the sprf, ovrf, and modf flags, the user can still service these interrupts after the spi has been disabled. the user can disable the spi by writing 0 to the spe bit. the spi can also be disabled by a mode fault occurring in an spi that wa s configured as a master with the modfen bit set. 15.3.6 error conditions the following flags signal spi error conditions: overflow (ovrf) ? failing to read the spi data register before the next full byte enters the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read. ovrf is in the spi status and control register. mode fault error (modf) ? the modf bit indicates that the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. modf is in the spi status and control register. 15.3.6.1 overflow error the overflow flag (ovrf) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of th e next transmission occurs. the bit 1 capture strobe occurs in the middle of spsck cycle 7 (see figure 15-4 and figure 15-6 .) if an overflow occurs, all data received after the overflow and before the ovrf bit is cleared does not transfer to the receive data register and does not set the spi receiver full bit (sprf). the unread data that transferred to the receive data register before the overflow occurred can still be read. therefore, an overflow error always indicates the loss of data. clear the overflow flag by reading the spi status and control register and then reading the spi data register. ovrf generates a receiver/error interrupt request if the error interrupt enable bit (errie) is also set. the sprf, modf, and ovrf interrupts share the same interrupt vector (see figure 15-11 .) it is not possible to enable modf or ovrf individually to generate a receiver/error interrupt request. however, leaving modfen low prevents modf from being set. if the sprf interrupt is enabled and the ovrf inte rrupt is not, watch for an overflow condition. figure 15-9 shows how it is possible to mi ss an overflow. the first part of figure 15-9 shows how it is possible to read the spscr and spdr to clear the sprf without problems. however, as illustrated by the second transmission example, the ovrf bit c an be set in between the time that spscr and spdr are read.
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 165 in this case, an overflow can be missed easily. because no more sprf interrupts can be generated until this ovrf is serviced, it is not obvious that bytes ar e being lost as more transmissions are completed. to prevent this, either enable the ovrf interrupt or do another read of the spscr following the read of the spdr. this ensures that the ovrf was not set before the sprf was cleared and that future transmissions can set the sprf bit. figure 15-10 illustrates this process. g enerally, to avoid this second spscr read, enable ovrf by setting the errie bit. figure 15-9. missed read of overflow condition figure 15-10. clearing sprf when ovrf interrupt is not enabled read read ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. read spscr with sprf bit set read byte 1 in spdr, byte 2 sets sprf bit. read spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. read byte 2 in spdr, clearing sprf bit, byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is not cleared. byte 4 is lost. and ovrf bit clear. and ovrf bit clear. spscr spdr read read ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. read spscr with sprf bit set read byte 1 in spdr, read spscr again byte 2 sets sprf bit. read spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. read byte 2 in spdr, read spscr again read byte 2 spdr, byte 4 sets sprf bit. read spscr. read byte 4 in spdr, read spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear. spscr spdr
serial peripheral in terface (spi) module mc68hc908qb8 data sheet, rev. 1 166 freescale semiconductor 15.3.6.2 mode fault error setting spmstr selects master mode and configures the spsck and mosi pins as outputs and the miso pin as an input. clearing spmstr selects sl ave mode and configures the spsck and mosi pins as inputs and the miso pin as an output. the mode fault bit, modf, becomes set any time the state of the slave select pin, ss , is inconsistent with the mode selected by spmstr. to prevent spi pin contention and damage to the mcu, a mode fault error occurs if: the ss pin of a slave spi goes high during a transmission the ss pin of a master spi goes low at any time for the modf flag to be set, the mode fault error enable bit (modfen) must be set. clearing the modfen bit does not clear the modf flag but does prevent modf from being set again after modf is cleared. modf generates a receiver/error interrupt request if the error interrupt enable bit (errie) is also set. the sprf, modf, and ovrf interrupts share the same interrupt vector. (see figure 15-11 .) it is not possible to enable modf or ovrf individually to generate a receiver/error interrupt request. however, leaving modfen low prevents modf from being set. in a master spi with the mode fault enable bit (modfe n) set, the mode fault flag (modf) is set if ss goes low. a mode fault in a master spi causes the following events to occur: if errie = 1, the spi generates an spi receiver/error interrupt request. the spe bit is cleared. the spte bit is set. the spi state counter is cleared. the data direction register of the shared i/o port regains control of port drivers. note to prevent bus contention with another master spi after a mode fault error, clear all spi bits of the data direction register of the shared i/o port before enabling the spi. when configured as a slave (spmstr = 0), the modf flag is set if ss goes high during a transmission. when cpha = 0, a transmission begins when ss goes low and ends after the incoming spsck goes to its idle level following the shift of the eighth data bit. when cpha = 1, the transmission begins when the spsck leaves its idle level and ss is already low. the transmission continues until the spsck returns to its idle level following the sh ift of the last data bit. see 15.3.3 transmission formats . note setting the modf flag does not clear the spmstr bit. spmstr has no function when spe = 0. reading spmstr when modf = 1 shows the difference between a modf occurring when the spi is a master and when it is a slave. when cpha = 0, a modf occurs if a slave is selected (ss is low) and later unselected (ss is high) even if no spsck is sent to that slave. this happens because ss low indicates the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then later unselected with no transmission occurring. therefore, modf does not occur because a transmission was never begun.
interrupts mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 167 in a slave spi (mstr = 0), modf generates an spi receiver/error interrupt request if the errie bit is set. the modf bit does not clear the spe bit or rese t the spi in any way. software can abort the spi transmission by clearing the spe bit of the slave. note a high on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. to clear the modf flag, read the spscr with the modf bit set and then write to the spcr register. this entire clearing mechanism must occur with no modf condition existing or else the flag is not cleared. 15.4 interrupts four spi status flags can be enabled to generate interrupt requests. see table 15-1 . reading the spi status and control register with sprf set and then reading the receive data register clears sprf. the clearing mechanism for the spte flag is requires only a write to the transmit data register. the spi transmitter interrupt enable bit (sptie) enabl es the spte flag to generate transmitter interrupt requests, provided that the spi is enabled (spe = 1). the spi receiver interrupt enable bit (sprie) enables sprf to generate receiver interrupt requests, regardless of the state of spe. see figure 15-11 . figure 15-11. spi interrupt request generation table 15-1. spi interrupts flag request spte transmitter empty spi transmitter interrupt request (sptie = 1, spe = 1) sprf receiver full spi receiver interrupt request (sprie = 1) ovrf overflow spi receiver/error interrupt request (errie = 1) modf mode fault spi receiver/error interrupt request (errie = 1) spte sptie sprf sprie spe interrupt request interrupt request spi transmitter spi receiver/error errie modf ovrf
serial peripheral in terface (spi) module mc68hc908qb8 data sheet, rev. 1 168 freescale semiconductor the error interrupt enable bit (errie) enables both the modf and ovrf bits to generate a receiver/error interrupt request. the mode fault enable bit (modfen) can prevent the modf flag from being set so that only the ovrf bit is enabled by the errie bit to generate receiver/error interrupt requests. the following sources in the spi status and control register can generate interrupt requests: spi receiver full bit (sprf) ? sprf becomes set ever y time a byte transfers from the shift register to the receive data register. if the spi receiver interrupt enable bit, sprie, is also set, sprf generates an spi receiver/error interrupt request. spi transmitter empty bit (spte) ? spte becomes set every time a byte transfers from the transmit data register to the shift register. if the spi transmit interrupt enable bit, sptie, is also set, spte generates an spte interrupt request. 15.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 15.5.1 wait mode the spi module remains active after the execution of a wait instruction. in wait mode the spi module registers are not accessible by the cpu. any enabled interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. to exit wait mode when an overflow condition occurs , enable the ovrf bit to generate interrupt requests by setting the error interrupt enable bit (errie). see 15.4 interrupts . 15.5.2 stop mode the spi module is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions. spi operation resumes after an external interrupt. if stop mode is exited by reset, any transfer in progress is aborted, and the spi is reset. 15.6 spi during break interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see bfcr in the sim section of this data sheet . to allow software to clear status bits during a break interrupt, write a 1 to bcfe. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to bcfe. with bcfe cleared (its default state), software can read and write registers during the break stat e without affecting status bits. some status bits have a two-step read/write clearing procedure. if softw are does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is cleared. after the break, doing the second step clears the status bit.
i/o signals mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 169 15.7 i/o signals the spi module can share its pins with the general-purpose i/o pins. see figure 15-1 for the port pins that are shared. the spi module has four i/o pins: miso ? master input/slave output mosi ? master output/slave input spsck ? serial clock ss ? slave select 15.7.1 miso (master in/slave out) miso is one of the two spi module pins that transmits se rial data. in full duplex operation, the miso pin of the master spi module is connected to the miso pin of the slave spi module. the master spi simultaneously receives data on its miso pin and transmits data from its mosi pin. slave output data on the miso pin is enabled only w hen the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is 0 and its ss pin is low. to support a multiple-slave system, a high on the ss pin puts the miso pin in a high-impedance state. when enabled, the spi controls data direction of the mi so pin regardless of the st ate of the data direction register of the shared i/o port. 15.7.2 mosi (mas ter out/slave in) mosi is one of the two spi module pins that transmits serial data. in full-duplex operation, the mosi pin of the master spi module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits data from its mosi pin and receives data on its miso pin. when enabled, the spi controls data direction of the mo si pin regardless of the st ate of the data direction register of the shared i/o port. 15.7.3 spsck (serial clock) the serial clock synchronizes data transmission between master and sl ave devices. in a master mcu, the spsck pin is the clock output. in a slave mcu, the spsck pin is the cl ock input. in full-duplex operation, the master and slave mcus exchange a byte of data in eight serial clock cycles. when enabled, the spi contro ls data direction of the spsck pin regardless of the state of the data direction register of the shared i/o port. 15.7.4 ss (slave select) the ss pin has various functions depending on the current state of the spi. for an spi configured as a slave, ss is used to select a slave. for cpha = 0, the ss is used to define the start of a transmission. (see 15.3.3 transmission formats .) because it is used to indicate the start of a transmission, ss must be toggled high and low between each byte transmitted for the cpha = 0 format. however, it can remain low between transmissions for the cpha = 1 format. see figure 15-12 .
serial peripheral in terface (spi) module mc68hc908qb8 data sheet, rev. 1 170 freescale semiconductor figure 15-12. cpha/ss timing when an spi is configured as a slave, the ss pin is always configured as an input. it cannot be used as a general-purpose i/o regardless of the state of the modfen control bit. however, the modfen bit can still prevent the state of ss from creating a modf error. see 15.8.2 spi status and control register. note a high on the ss pin of a slave spi puts the miso pin in a high-impedance state. the slave spi ignores all inco ming spsck clocks, even if it was already in the middle of a transmission. when an spi is configured as a master, the ss input can be used in conjunc tion with the modf flag to prevent multiple masters from driving mosi and spsck. (see 15.3.6.2 mode fault error .) for the state of the ss pin to set the modf flag, the modfen bit in the spsck register must be set. if the modfen bit is 0 for an spi master, the ss pin can be used as a general-purpose i/o under the control of the data direction register of the shared i/o port. when modfen is 1, it is an input-only pin to the spi regardless of the state of the data direction register of the shared i/o port. user software can read the state of the ss pin by configuring the appropri ate pin as an input and reading the port data register. see table 15-2. 15.8 registers the following registers allow the user to control and monitor spi operation: spi control register (spcr) spi status and control register (spscr) spi data register (spdr) table 15-2. spi configuration spe spmstr modfen spi configuration function of ss pin 0 x (1) 1. x = don?t care x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input-only to spi 1 1 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input-only to spi byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1
registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 171 15.8.1 spi c ontrol register the spi control register: enables spi module interrupt requests configures the spi module as master or slave selects serial clock polarity and phase configures the spsck, mosi, and miso pins as open-drain outputs enables the spi module sprie ? spi receiver interrupt enable bit this read/write bit enables interrupt requests generated by the sprf bit. the sprf bit is set when a byte transfers from the shift register to the receive data register. 1 = sprf interrupt requests enabled 0 = sprf interrupt requests disabled spmstr ? spi master bit this read/write bit selects master mode operation or slave mode operation. 1 = master mode 0 = slave mode cpol ? clock polarity bit this read/write bit determines the logic stat e of the spsck pin betw een transmissions. (see figure 15-4 and figure 15-6 .) to transmit data between spi modules, the spi modules must have identical cpol values. cpha ? clock phase bit this read/write bit controls the timing relationship between the serial clock and spi data. (see figure 15-4 and figure 15-6 .) to transmit data between spi modules, the spi modules must have identical cpha values. when cpha = 0, the ss pin of the slave spi module must be high between bytes. (see figure 15-12 .) spwom ? spi wired-or mode bit this read/write bit configures pi ns spsck, mosi, and miso so that these pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull spsc k, mosi, and miso pins spe ? spi enable this read/write bit enabl es the spi module. clearin g spe causes a partial reset of the spi. (see 15.3.5 resetting the spi .) 1 = spi module enabled 0 = spi module disabled bit 7654321bit 0 read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 r = reserved figure 15-13. spi control register (spcr)
serial peripheral in terface (spi) module mc68hc908qb8 data sheet, rev. 1 172 freescale semiconductor sptie? spi transmit interrupt enable this read/write bit enables interrupt requests generated by the spte bit. spte is set when a byte transfers from the transmit data register to the shift register. 1 = spte interrupt requests enabled 0 = spte interrupt requests disabled 15.8.2 spi status and control register the spi status and control register c ontains flags to si gnal these conditions: receive data register full failure to clear sprf bit before next byte is received (overflow error) inconsistent logic level on ss pin (mode fault error) transmit data register empty the spi status and control register also c ontains bits that perform these functions: enable error interrupts enable mode fault error detection select master spi baud rate sprf ? spi receiver full bit this clearable, read-only flag is set each time a byte tr ansfers from the shift register to the receive data register. sprf generates a interrupt request if the sp rie bit in the spi control register is set also. during an sprf interrupt, user software can clear sprf by reading the spi status and control register with sprf set followed by a read of the spi data register. 1 = receive data register full 0 = receive data register not full errie ? error interrupt enable bit this read/write bit enables the modf and ovrf bits to generate interrupt requests. 1 = modf and ovrf can generate interrupt requests 0 = modf and ovrf cannot generate interrupt requests ovrf ? overflow bit this clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. in an ov erflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and then reading the receive data register. 1 = overflow 0 = no overflow bit 7654321bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 = unimplemented figure 15-14. spi status and control register (spscr)
registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 173 modf ? mode fault bit this clearable, read-only flag is set in a slave spi if the ss pin goes high during a transmission with modfen set. in a master spi, the modf flag is set if the ss pin goes low at any time with the modfen bit set. clear modf by reading the spi stat us and control register (spscr) with modf set and then writing to the spi control register (spcr). 1 = ss pin at inappropriate logic level 0 = ss pin at appropriate logic level spte ? spi transmitter empty bit this clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. spte generates an spte interrupt request if the sptie bit in the spi control register is also set. note do not write to the spi data register unless spte is high. during an spte interrupt, user software can clear spte by writing to the transmit data register. 1 = transmit data register empty 0 = transmit data register not empty modfen ? mode fault enable bit this read/write bit, when set, allows the modf flag to be set. if the modf flag is set, clearing modfen does not clear the modf flag. if the spi is enabled as a master and the modfen bit is 0, then the ss pin is available as a general-purpose i/o. if the modfen bit is 1, then this pin is not av ailable as a general-purpo se i/o. when the spi is enabled as a slave, the ss pin is not available as a general-purpose i/o regardless of the value of modfen. see 15.7.4 ss (slave select). if the modfen bit is 0, the level of the ss pin does not affect the operation of an enabled spi configured as a master. for an enabled spi configured as a slave, having modfen low only prevents the modf flag from being set. it does not affect any other part of spi operation. see 15.3.6.2 mode fault error. spr1 and spr0 ? spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 15-3 . spr1 and spr0 have no effect in slave mode. use this formula to calculate the spi baud rate: table 15-3. spi master baud rate selection spr1 and spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 baud rate = busclk bd
serial peripheral in terface (spi) module mc68hc908qb8 data sheet, rev. 1 174 freescale semiconductor 15.8.3 spi data register the spi data register consists of the read-only receive data register and the write-only transmit data register. writing to the spi data register writes dat a into the transmit data register. reading the spi data register reads data from the receive data register. the transmit data and receive data registers are separate registers that can c ontain different values. see figure 15-2 . r7?r0/t7?t0 ? receive/transmit data bits note do not use read-modify-write instructi ons on the spi data register because the register read is not the same as the register written. bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 15-15. spi data register (spdr)
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 175 chapter 16 timer interface module (tim) 16.1 introduction this section describes the timer interface module (tim). the tim module is a 4-channel timer that provides a timing reference with input capture, out put compare, and pulse-width-modulation functions. the tim module shares its pins with general -purpose input/output (i/o) port pins. see figure 16-1 for port location of these shared pins. 16.2 features features include the following: four input capture/output compare channels ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered output compare pulse-width modulation (pwm) signal generation programmable clock input ? 7-frequency internal bus clock prescaler selection ? external clock input pin if available, see figure 16-1 free-running or modulo up-count operation toggle any channel pin on overflow counter stop and reset bits 16.3 functional description figure 16-2 shows the structure of the tim. the central component of the tim is the 16-bit counter that can operate as a free-running counter or a modulo up- counter. the counter provides the timing reference for the input capture and output compare functions. the tim counter modulo registers, tmodh:tmodl, control the modulo value of the counter. software can read the counter value, tcnth:tcntl, at any time without affecting the counting sequence. the four tim channels are programmable independently as input capture or output compare channels. 16.3.1 tim counter prescaler the tim clock source is one of the seven prescaler outputs or the external clock input pin, tclk if available. the prescaler generates seven clock rates fr om the internal bus clock. the prescaler select bits, ps[2:0], in the tim status and control register (tsc) select the clock source.
timer interface module (tim) mc68hc908qb8 data sheet, rev. 1 176 freescale semiconductor figure 16-1. block diagram highlighting tim block and pins 16.3.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture chann el, the tim latches the contents of the counter into the tim channel registers, tchxh:tchxl. the polar ity of the active edge is programmable. input captures can be enabled to generate interrupt requests. rst , irq : pins have internal pull up device all port pins have prog rammable pull up device pta[0:5]: higher current sink and source capability pta0/tch0/ad0/kbi0 pta1/tch1/ad1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 4-channel 16-bit timer module keyboard interrupt module external interrupt module auto wakeup low-voltage inhibit cop module 10-channel 10-bit adc enhanced serial ptb0/sck/ad4 ptb ddrb m68hc08 cpu pta ddra ptb1/mosi/ad5 ptb2/miso/ad6 ptb3/ss /ad7 ptb4/rxd/ad8 ptb5/txd/ad9 ptb6/tch2 ptb7/tch3 power supply v dd v ss clock generator communications interface module module serial peripheral interface mc68hc908qb8 8192 bytes user flash 256 bytes user ram mc68hc908qb8 monitor rom break module development support
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 177 figure 16-2. tim block diagram 16.3.3 output compare with the output compare function, the tim can generat e a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare prescaler prescaler select 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch ms0a els0b els0a tof toie 16-bit comparator 16-bit latch channel 0 channel 1 trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b internal bus ms1a internal bus clock interrupt logic port logic interrupt logic interrupt logic port logic (if available) 16-bit counter 16-bit comparator 16-bit latch ms2a els2b els2a 16-bit comparator 16-bit latch channel 2 channel 3 tov2 ch2ie ch2f els3b els3a tov3 ch3ie ch3max ch3f ch2max ms2b ms3a tch3 tch2 tch1 tch0 tch3h:tch3l tch2h:tch2l tch1h:tch1l tch0h:tch0l tmodh:tmodl tcnth:tcntl tclk tclk interrupt logic port logic interrupt logic port logic
timer interface module (tim) mc68hc908qb8 data sheet, rev. 1 178 freescale semiconductor channel, the tim can set, clear, or toggle the channel pin. output compares can be enabled to generate interrupt requests. 16.3.3.1 unbuffered output compare any output compare channel can generate unbuffer ed output compare pulses as described in 16.3.3 output compare . the pulses are unbuffered because changing t he output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overfl ow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchronize unbuffer ed changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt rout ine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 16.3.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of t he linked pair alternately control the output. setting the ms0b bit in tim channel 0 status and control register (tsc 0) links channel 0 and channel 1. the output compare value in the tim channel 0 register s initially controls the output on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the output after the tim overflows. at each subsequent ov erflow, the tim channel registers (0 or 1) that control the output are the ones written to last. ts c0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the tch2 pin. the tim channel registers of t he linked pair alternately control the output. setting the ms2b bit in tim channel 2 status and control register (tsc 2) links channel 2 and channel 3. the output compare value in the tim channel 2 register s initially controls the output on the tch2 pin. writing to the tim channel 3 registers enables the tim channel 3 registers to synchronously control the output after the tim overflows. at each subsequent ov erflow, the tim channel registers (2 or 3) that control the output are the ones written to last. ts c2 controls and monitors the buffered output compare function, and tim channel 3 status and control register (tsc3) is unused. while the ms2b bit is set, the channel 3 pin, tch3, is available as a general-purpose i/o pin. note in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 179 the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 16.3.4 pulse widt h modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo regi sters determines the period of the pwm signal. the channel pin toggles when the counter reaches the valu e in the tim counter modulo registers. the time between overflows is the period of the pwm signal. as figure 16-3 shows, the output compare value in the tim channel registers determines the pulse width of the pwm signal. the time between overflow and out put compare is the pulse width. program the tim to clear the channel pin on output compare if the polarity of the pwm pulse is 1 (elsxa = 0). program the tim to set the pin if the polarity of the pwm pulse is 0 (elsxa = 1). the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is 000. see 16.8.1 tim status and control register . the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50%. figure 16-3. pwm period and pulse width 16.3.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 16.3.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new va lue prevents any compare during that pwm period. also, using a tim overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tim may pass the new value before it is written to the timer channel (tchxh:tchxl). period pulse width overflow overflow overflow output compare output compare output compare polarity = 1 (elsxa = 0) polarity = 0 (elsxa = 1) tchx tchx
timer interface module (tim) mc68hc908qb8 data sheet, rev. 1 180 freescale semiconductor use the following methods to synchronize unbuffer ed changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 16.3.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the output. setting the ms0b bit in tim channel 0 status and control register (tsc 0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to sy nchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 controls and monitors the buffered pwm function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered pwm channel whose output appears on the tch2 pin. the tim channel registers of the linked pair alternately control the output. setting the ms2b bit in tim channel 2 status and control register (tsc 2) links channel 2 and channel 3. the tim channel 2 registers initially control the pulse width on the tch2 pin. writing to the tim channel 3 registers enables the tim channel 3 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (2 or 3) that control the pulse width are the ones written to last. tsc2 controls and monitors the buffered pwm function, and tim channel 3 status and control register (tsc3) is unused. while the ms2b bit is set, the channel 3 pin, tch3, is available as a general-purpose i/o pin. note in buffered pwm signal generation, do not write new pulse width values to the currently active channel regist ers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals.
functional description mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 181 16.3.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tim status and control register (tsc): a. stop the counter by setting the tim stop bit, tstop. b. reset the counter and prescaler by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (tchxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode se lect bits, msxb:msxa. see table 16-2 . b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (polarity 1 ? to clear output on compare) or 1:1 (polarity 0 ? to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. see table 16-2 . note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control register (tsc), clear the tim stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0h:tch0l) initially control the buffered pwm output. tim status control register 0 (tsc0) controls and monitors the pwm si gnal from the linked channels. ms0b takes priority over ms0a. setting ms2b links channels 2 and 3 and configures them for buffered pwm operation. the tim channel 2 registers (tch2h:tch2l) initially control the buffered pwm output. tim status control register 2 (tsc2) controls and monitors the pwm si gnal from the linked channels. ms2b takes priority over ms2a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. see 16.8.4 tim channel status and control registers .
timer interface module (tim) mc68hc908qb8 data sheet, rev. 1 182 freescale semiconductor 16.4 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? the tof bit is set when the counter reaches the modulo value programmed in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow interrupt requests. tof and toie are in the tsc register. tim channel flags (ch3f:ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim interrupt r equests are controlled by the channel x interrupt enable bit, chxie. channel x tim interrupt requests are enabled when chxie =1. chxf and chxie are in the tscx register. 16.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 16.5.1 wait mode the tim remains active after the execution of a wait instruction. in wait mode the tim registers are not accessible by the cpu. any enabled interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, r educe power consumption by stopping the tim before executing the wait instruction. 16.5.2 stop mode the tim module is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions. tim operation resumes after an external interrupt. if stop mode is exited by reset, the tim is reset. 16.6 tim during break interrupts a break interrupt stops the counter. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see bfcr in the sim section of this data sheet . to allow software to clear status bits during a break interrupt, write a 1 to bcfe. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to bcfe. with bcfe cleared (its default state), software can read and write registers during the break stat e without affecting status bits. some status bits have a two-step read/write clearing procedure. if softw are does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is cleared. after the break, doing the second step clears the status bit.
i/o signals mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 183 16.7 i/o signals the tim module can share its pins wi th the general-purpose i/o pins. see figure 16-1 for the port pins that are shared. 16.7.1 tim channel i/ o pins (tch3:tch0) each channel i/o pin is programmable independently as an input capture pin or an output compare pin. tch0 and tch2 can be configured as buffered output compare or buffered pwm pins. 16.7.2 tim clock pin (tclk) tclk is an external clock input that can be the cl ock source for the counter instead of the prescaled internal bus clock. select the tclk input by writing 1s to the three prescaler select bits, ps[2:0]. (see 16.8.1 tim status and control register .) the minimum tclk pulse width is specified in 18.16 timer interface module characteristics . the maximum tclk frequency is the least of 4 mhz or bus frequency 2. 16.8 registers the following registers control and monitor operation of the tim: ? tim status and control register (tsc) tim control registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and control registers (tsc0 through tsc3) tim channel registers (tch0h:tch0l through tch3h:tch3l) 16.8.1 tim status and control register the tim status and control register (tsc) does the following: enables tim overflow interrupts flags tim overflows stops the counter resets the counter prescales the counter clock tof ? tim overflow flag bit this read/write flag is set when the counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tsc regist er when tof is set and then writing a 0 to tof. if another tim overflow occurs before the clearing sequence is complete, then writing 0 to tof has no bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 16-4. tim status and control register (tsc)
timer interface module (tim) mc68hc908qb8 data sheet, rev. 1 184 freescale semiconductor effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. writing a 1 to tof has no effect. 1 = counter has reached modulo value 0 = counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bit enables tim overflow interrupts when the tof bit becomes set. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled tstop ? tim stop bit this read/write bit stops the counter. counting re sumes when tstop is cleared. reset sets the tstop bit, stopping the counter unt il software clears the tstop bit. 1 = counter stopped 0 = counter active note do not set the tstop bit before entering wait mode if the tim is required to exit wait mode. also, when the tstop bit is set and the timer is configured for input capture operation, i nput captures are inhibited until the tstop bit is cleared. when using tsop to stop the timer counter, see if any timer flags are set. if a timer flag is set, it must be clea red by clearing tstop, then clearing the flag, then setting tstop again. trst ? tim reset bit setting this write-only bit resets the counter and the tim prescaler. setting trst has no effect on any other timer registers. counting resumes from $0000. trst is cleared automatically after the counter is reset and always reads as 0. 1 = prescaler and counter cleared 0 = no effect note setting the tstop and trst bits simultaneously stops the counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the counter as table 16-1 shows. table 16-1. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 1 1 1 tclk (if available)
registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 185 16.8.2 tim counter registers the two read-only tim counter registers contain the high and low bytes of the value in the counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latched during the break. 16.8.3 tim counter modulo registers the read/write tim modulo registers contain the m odulo value for the counter. when the counter reaches the modulo value, the overflow flag (tof) becomes set, and the counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmo dh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim counter modulo registers. note reset the counter before writing to the tim counter modulo registers. bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 = unimplemented figure 16-5. tim counter high register (tcnth) bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 16-6. tim counter low register (tcntl) bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 figure 16-7. tim counter modulo high register (tmodh) bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 figure 16-8. tim counter modulo low register (tmodl)
timer interface module (tim) mc68hc908qb8 data sheet, rev. 1 186 freescale semiconductor 16.8.4 tim channel status and control registers each of the tim channel status and control registers does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on tim overflow selects 0% and 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output com pare channel, chxf is set when the value in the counter registers matches the value in the tim channel x registers. clear chxf by reading the tscx register with chxf set and then writing a 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 figure 16-9. tim channel 0 status and control register (tsc0) bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 figure 16-10. tim channel 1 status and control register (tsc1) bit 7654321bit 0 read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 figure 16-11. tim channel 2 status and control register (tsc2) bit 7654321bit 0 read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset:00000000 = unimplemented figure 16-12. tim channel 3 status and control register (tsc3)
registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 187 writing a 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables tim interrupt service requests on channel x. 1 = channel x interrupt requests enabled 0 = channel x interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compar e/pwm operation. msxb exists only in the tsc0 and tsc2 registers. setting ms0b causes the contents of tsc1 to be ignored by the tim and reverts tch1 to general-purpose i/o. setting ms2b causes the contents of tsc3 to be ignored by the tim and reverts tch3 to general-purpose i/o. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 16-2 . 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tchx pin (see table 16-2 ). 1 = initial output level low 0 = initial output level high note before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tim status and control register (tsc). table 16-2. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 0 output compare or pwm software compare only 0 1 0 1 toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare
timer interface module (tim) mc68hc908qb8 data sheet, rev. 1 188 freescale semiconductor elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/ write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to an i/o port, and pin tchx is available as a general-purpose i/o pin. table 16-2 shows how elsxb and elsxa work. note after initially enabling a tim channel register for input capture operation and selecting the edge sensitivity, clear chxf to ignore any erroneous edge detection flags. tovx ? toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the counter overflows. when channel x is an input capture channel, tovx has no effect. 1 = channel x pin toggles on counter overflow. 0 = channel x pin does not toggle on counter overflow. note when tovx is set, a counter overflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at 1, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 16-13 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 16-13. chxmax latency 16.8.5 tim channel registers these read/write registers contain the captured counter value of the input capture function or the output compare value of the output compare function. the state of the tim channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading th e high byte of the tim channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. output overflow period chxmax overflow overflow overflow overflow compare output compare output compare output compare tchx
registers mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 189 in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x registers (tchxh) inhibits output compares until the low byte (tchxl) is written. bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset figure 16-14. tim channel x register high (tchxh) bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 16-15. tim channel x register low (tchxl)
timer interface module (tim) mc68hc908qb8 data sheet, rev. 1 190 freescale semiconductor
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 191 chapter 17 development support 17.1 introduction this section describes the break module, the mo nitor module (mon), and the monitor mode entry methods. 17.2 break module (brk) the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. features include: accessible input/output (i/o) registers during the break interrupt central processor unit (cpu) generated break interrupts software-generated break interrupts computer operating properly (cop ) disabling during break interrupts 17.2.1 functional description when the internal address bus matches the value writt en in the break address registers, the break module issues a breakpoint signal (bkpt ) to the system integration module (sim). the sim then causes the cpu to load the instruction register with a software interrupt instruction (swi). the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu generated address (the address in the program counter) matches the contents of the break address registers. software writes a 1 to the brka bit in the break status and control register. when a cpu generated address matches the contents of t he break address registers, the break interrupt is generated. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the microcontroller unit (mcu) to normal operation. figure 17-2 shows the structure of the break module. when the internal address bus matches the value writt en in the break address registers or when software writes a 1 to the brka bit in the break status and c ontrol register, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode)
development support mc68hc908qb8 data sheet, rev. 1 192 freescale semiconductor figure 17-1. block diagram highlighting brk and mon blocks rst , irq : pins have internal pull up device all port pins have prog rammable pull up device pta[0:5]: higher current sink and source capability pta0/tch0/ad0/kbi0 pta1/tch1/ad1/kbi1 pta2/irq /kbi2/tclk pta3/rst /kbi3 pta4/osc2/ad2/kbi4 pta5/osc1/ad3/kbi5 4-channel 16-bit timer module keyboard interrupt module single interrupt module auto wakeup low-voltage inhibit cop module 10-channel 10-bit adc enhanced serial ptb0/spsck/ad4 ptb ddrb m68hc08 cpu pta ddra ptb1/mosi/ad5 ptb2/miso/ad6 ptb3/ss /ad7 ptb4/rxd/ad8 ptb5/txd/ad9 ptb6/tch2 ptb7/tch3 mc68hc908qb8 power supply v dd v ss clock generator communications interface module module serial peripheral interface 8192 bytes user flash 256 bytes user ram mc68hc908qb8 monitor rom break module development support
break module (brk) mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 193 figure 17-2. break module block diagram the break interrupt timing is: when a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. when a break address is placed at an address of an instruction operand, the instruction is executed before the break interrupt. when software writes a 1 to the brka bit, the break interrupt occurs just before the next instruction is executed. by updating a break address and clearing the brka bit in a break interrupt routine, a break interrupt can be generated continuously. caution a break address should be placed at the address of the instruction opcode. when software does not change the break address and clears the brka bit in the first break interrupt routi ne, the next break interrupt will not be generated after exiting the interrupt routine even when the internal address bus matches the value written in the break address registers. 17.2.1.1 flag protection during break interrupts the system integration module (sim) controls whether or not module status bits can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see 14.8.2 break flag control register and the break interrupts subsection for each module. 17.2.1.2 tim during break interrupts a break interrupt stops the timer counter. 17.2.1.3 cop during break interrupts the cop is disabled during a break interrupt in mo nitor mode when the bdcop bit is set in the break auxiliary register (brkar). address bus[15:8] address bus[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high address bus[15:0] bkpt (to sim)
development support mc68hc908qb8 data sheet, rev. 1 194 freescale semiconductor 17.2.2 break module registers these registers control and monitor operation of the break module: break status and control register (brkscr) break address register high (brkh) break address register low (brkl) break status register (bsr) break flag control register (bfcr) 17.2.2.1 break status and control register the break status and control register (brkscr) contains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break addres s register matches. clear brke by writing a 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a 1 to brka generates a break interrupt. clear brka by writing a 0 to it before exiting the break routine. reset clears the brka bit. 1 = break address match 0 = no break address match 17.2.2.2 break address registers the break address registers (brkh and brkl) contai n the high and low bytes of the desired breakpoint address. reset clears the break address registers. bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 17-3. break status and control register (brkscr) bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 figure 17-4. break address register high (brkh) bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 17-5. break address register low (brkl)
break module (brk) mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 195 17.2.2.3 break auxiliary register the break auxiliary register (brkar) contains a bit that enables software to disable the cop while the mcu is in a state of break interrupt with monitor mode. bdcop ? break disable cop bit this read/write bit disables the cop during a break interrupt. reset clears the bdcop bit. 1 = cop disabled during break interrupt 0 = cop enabled during break interrupt 17.2.2.4 break status register the break status register (bsr) contains a flag to i ndicate that a break caused an exit from wait mode. this register is only used in emulation mode. sbsw ? sim break stop/wait sbsw can be read within the break state swi routine. the user can modify the return address on the stack by subtracting one from it. 1 = wait mode was exited by break interrupt 0 = wait mode was not exited by break interrupt 17.2.2.5 break flag control register the break control register (bfcr) contains a bit that enables software to clear status bits while the mcu is in a break state. bit 7654321bit 0 read:0000000 bdcop write: reset:00000000 = unimplemented figure 17-6. break auxiliary register (brkar) bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset: 0 r = reserved 1. writing a 0 clears sbsw. figure 17-7. break status register (bsr) bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r = reserved figure 17-8. break flag control register (bfcr)
development support mc68hc908qb8 data sheet, rev. 1 196 freescale semiconductor bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break 17.2.3 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. if enabled, the break module will remain enabled in wait and stop mo des. however, since the internal address bus does not increment in these modes, a break interrupt will never be triggered. 17.3 monitor module (mon) the monitor module allows debugging and programmin g of the microcontroller unit (mcu) through a single-wire interface with a host computer. monitor mode entry can be achieved without use of the higher test voltage, v tst , as long as vector addresses $fffe and $ffff are blank, thus reducing the hardware requirements for in-circuit programming. features include: normal user-mode pin functionality one pin dedicated to serial communi cation between mcu and host computer standard non-return-to-zero (nrz) communication with host computer standard communication baud rate (7200 @ 2-mhz bus frequency) execution of code in random-a ccess memory (ram) or flash flash memory security feature (1) flash memory programming interface use of external 9.8304 mhz oscillator to generate internal frequency of 2.4576 mhz simple internal oscillator mode of operat ion (no external clock or high voltage) monitor mode entry without high voltage, v tst , if reset vector is blank ($fffe and $ffff contain $ff) normal monitor mode entry if v tst is applied to irq 17.3.1 functional description figure 17-9 shows a simplified diagram of monitor mode entry. the monitor module receives and exec utes commands from a host computer. figure 17-10 , figure 17-11 , and figure 17-12 show example circuits used to enter m onitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute code downloaded into ram by a host computer wh ile most mcu pins retain normal operating mode functions. all communicati on between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pullup resistor. 1. no security feature is absolutely secure . however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users.
monitor module (mon) mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 197 figure 17-9. simplified monitor mode entry flowchart monitor mode entry por reset pta0 = 1, pta1 = 1, and pta4 = 0? irq = v tst ? yes no yes no forced monitor mode normal user mode normal monitor mode invalid user mode no no host sends 8 security bytes is reset por? yes yes yes no are all security bytes correct? no yes enable flash disable flash execute monitor code does reset occur? conditions from table 17-1 debugging and flash programming (if flash is enabled) pta0 = 1, reset vector blank?
development support mc68hc908qb8 data sheet, rev. 1 198 freescale semiconductor figure 17-10. monitor mode circuit (external clock, with high voltage) figure 17-11. monitor mode circuit (external clock, no high voltage) 9.8304 mhz clock + 10 k ? * v dd 10 k ? * rst (pta3) irq (pta2) pta0 osc1 (pta5) 8 7 db9 2 3 5 16 15 2 6 10 9 v dd max232 v+ v? 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? pta1 pta4 v ss 0.1 f v dd 1 k ? 9.1 v c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + 1 f v dd + 1 f v tst * value not critical v dd v dd 10 k ? * rst (pta3) irq (pta2) pta0 osc1 (pta5) 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 1 f max232 v+ v? v dd 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? n.c. pta1 n.c. pta4 v ss 0.1 f v dd 9.8304 mhz clock c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + + + 1 f v dd 10 k ? * * value not critical n.c.
monitor module (mon) mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 199 figure 17-12. monitor mode circuit (internal clock, no high voltage) the monitor code has been updated from previous ve rsions of the monitor code to allow enabling the internal oscillator to generate the internal cl ock. this addition, wh ich is enabled when irq is held low out of reset, is intended to support serial communication/ programming at 9600 baud in monitor mode by using the internal oscillator, and the internal oscillator user trim value osctrim (flash location $ffc0, if programmed) to generate the desired internal frequenc y (3.2 mhz). since this feature is enabled only when irq is held low out of reset, it cannot be used when the reset vector is programmed (i.e., the value is not $ffff) because entry into monitor mode in this case requires v tst on irq . the irq pin must remain low during this monitor session in order to maintain communication. table 17-1 shows the pin conditions for entering monitor mo de. as specified in the table, monitor mode may be entered after a power-on reset (por) and will allow communication at 9600 baud provided one of the following sets of conditions is met: if $fffe and $ffff do not contain $ff (programmed state): ? the external clock is 9.8304 mhz ?irq = v tst if $fffe and $ffff contain $ff (erased state): ? the external clock is 9.8304 mhz ?irq = v dd (this can be implemented through the internal irq pullup) if $fffe and $ffff contain $ff (erased state): ?irq = v ss (internal oscillator is select ed, no external clock required) the rising edge of the internal rst signal latches the monitor mode. once monitor mode is latched, the values on pta1 and pta4 pins can be changed. once out of reset, the mcu waits for the host to send eight security bytes (see 17.3.2 security ). after the security bytes, the mcu sends a break signal (10 consecut ive 0s) to the host, indicating that it is ready to receive a command. rst (pta3) irq (pta2) pta0 10 k ? * osc1 (pta5) n.c. 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 1 f max232 c1+ c1? v+ v? 5 4 1 f c2+ c2? v dd 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? n.c. pta1 n.c. pta4 v ss 0.1 f v dd + 3 1 1 f + + + 1 f v dd * value not critical n.c.
development support mc68hc908qb8 data sheet, rev. 1 200 freescale semiconductor 17.3.1.1 normal monitor mode rst and osc1 functions will be active on the pt a3 and pta5 pins respectively as long as v tst is applied to the irq pin. if the irq pin is lowered (no longer v tst ) then the chip will still be operating in monitor mode, but the pin functions will be determi ned by the settings in the c onfiguration registers (see chapter 5 configuration register (config) ) when v tst was lowered. with v tst lowered, the bih and bil instructions will read the irq pin state only if irqen is set in the config2 register. if monitor mode was entered with v tst on irq , then the cop is disabled as long as v tst is applied to irq . table 17-1. monitor mode signal requirements and options mode irq (pta2) rst (pta3) reset vector serial communi- cation mode selection cop communication speed comments pta0 pta1 pta4 external clock bus frequency baud rate normal monitor v tst v dd x110disabled 9.8304 mhz 2.4576 mhz 9600 provide external clock at osc1. forced monitor v dd x $ffff (blank) 1xxdisabled 9.8304 mhz 2.4576 mhz 9600 provide external clock at osc1. v ss x $ffff (blank) 1xxdisabledx 3.2 mhz (trimmed) 9600 internal clock is active. user x x not $ffff x x x enabled x x x mon08 function [pin no.] v tst [6] rst [4] ? com [8] mod0 [12] mod1 [10] ? osc1 [13] ?? 1. pta0 must have a pullup resistor to v dd in monitor mode. 2. communication speed in the table is an example to obtain a baud rate of 9600. baud rate using external oscillator is bus frequency / 256 and baud rate using internal oscillator is bus frequency / 335. 3. external clock is a 9.8304 mhz oscillator on osc1. 4. lowering v tst once monitor mode is entered allows the clock so urce to be controlled by the oscsc register. 5. x = don?t care 6. mon08 pin refers to p&e microcomputer sy stems? mon08-cyclone 2 by 8-pin connector. nc 1 2 gnd nc 3 4 rst nc 5 6 irq nc 7 8 pta0 nc 9 10 pta4 nc 11 12 pta1 osc1 13 14 nc v dd 15 16 nc
monitor module (mon) mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 201 17.3.1.2 forced monitor mode if entering monitor mode wit hout high voltage on irq , then startup port pin requirements and conditions, (pta1/pta4) are not in effect. this is to reduce circuit requirements when performing in-circuit programming. note if the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial power-on reset (por). once the reset vector has been programmed, the traditional method of applying a voltage, v tst , to irq must be used to enter monitor mode. if monitor mode was entered as a result of the reset vector being blank, the cop is always disabled regardless of the state of irq . if the voltage applied to the irq is less than v tst , the mcu will come out of reset in user mode. internal circuitry monitors the reset vector fetches and will assert an internal reset if it detects that the reset vectors are erased ($ff). when the mcu comes out of reset, it is forced into monitor mode without requiring high voltage on the irq pin. once out of reset, the monitor code is in itially executing with the internal clock at its default frequency. if irq is held high, all pins will default to regular i nput port functions except for pta0 and pta5 which will operate as a serial communication port and osc1 input respectively (refer to figure 17-11 ). that will allow the clock to be driven from an ex ternal source through osc1 pin. if irq is held low, all pins will default to regular input port function except for pta0 which will operate as serial communication port. refer to figure 17-12 . regardless of the state of the irq pin, it will not function as a port input pin in monitor mode. bit 2 of the port a data register will always read 0. the bih and bil instructions will behave as if the irq pin is enabled, regardless of the settings in the configuration register. see chapter 5 configuration register (config) . the cop module is disabled in forced monitor mode. any reset other than a power-on reset (por) will automatically force the mc u to come back to the forced monitor mode. 17.3.1.3 monitor vectors in monitor mode, the mcu uses different vectors for reset, swi (software interrupt), and break interrupt than those for user mode. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. note exiting monitor mode after it has been initiated by having a blank reset vector requires a power-on reset (por). pulling rst (when rst pin available) low will not exit monitor mode in this situation. table 17-2 summarizes the differences between user mode and monitor mode regarding vectors. table 17-2. mode difference modes functions reset vector high reset vector low break vector high break vector low swi vector high swi vector low user $fffe $ffff $fffc $fffd $fffc $fffd monitor $fefe $feff $fefc $fefd $fefc $fefd
development support mc68hc908qb8 data sheet, rev. 1 202 freescale semiconductor 17.3.1.4 data format communication with the monitor rom is in standard non-return-to-zero (nrz) ma rk/space data format. transmit and receive baud rates must be identical. figure 17-13. monitor data format 17.3.1.5 break signal a start bit (logic 0) followed by nine logic 0 bits is a break signal. when the monitor receives a break signal, it drives the pta0 pin high for the duration of tw o bits and then echoes back the break signal. figure 17-14. break transaction 17.3.1.6 baud rate the monitor communication baud rate is controlled by t he frequency of the external or internal oscillator and the state of the appropriate pins as shown in table 17-1 . table 17-1 also lists the bus frequencies to achieve standard baud rates. the effective baud rate is the bus frequency divided by 256 wh en using an external oscillator. when using the internal oscillator in forced monitor mode, the effective baud rate is the bus frequency divided by 335. 17.3.1.7 commands the monitor rom firmware uses these commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) the monitor rom firmware echoes each received byte back to the pta0 pin for error checking. an 11-bit delay at the end of each command allows the host to send a break character to cancel the command. a delay of two bit times occurs before each echo and before read, iread, or readsp data is returned. the data returned by a read command appears after the echo of the last byte of the command. note wait one bit time after each echo before sending the next byte. bit 5 start bit bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 7 bit 0 bit 6 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit 2-stop bit delay before zero echo
monitor module (mon) mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 203 figure 17-15. read transaction figure 17-16. write transaction a brief description of each monitor mode command is given in table 17-3 through table 17-8 . table 17-3. read (read memory) command description read byte from memory operand 2-byte address in high-byte:low-byte order data returned returns contents of specified address opcode $4a command sequence read read echo from host address high address high address low address low data return 13, 2 11 4 4 notes: 2 = data return delay, approximately 2 bit times 3 = cancel command delay, 11 bit times 4 = wait 1 bit time before sending next byte. 44 1 = echo delay, approximately 2 bit times write write echo from host address high address high address low address low data data notes: 2 = cancel command delay, 11 bit times 3 = wait 1 bit time before sending next byte. 11 3 11 3 3 32, 3 1 = echo delay, approximately 2 bit times read read echo sent to monitor address high address high address low data return address low
development support mc68hc908qb8 data sheet, rev. 1 204 freescale semiconductor a sequence of iread or iwrite commands can acce ss a block of memory sequentially over the full 64-kbyte memory map. table 17-4. write (write memory) command description write byte to memory operand 2-byte address in high-byte:low-by te order; low byte followed by data byte data returned none opcode $49 command sequence table 17-5. iread (indexed read) command description read next 2 bytes in me mory from last address accessed operand none data returned returns contents of next two addresses opcode $1a command sequence table 17-6. iwrite (indexed write) command description write to la st address accessed + 1 operand single data byte data returned none opcode $19 command sequence write write echo from host address high address high address low address low data data iread iread echo data return data from host iwrite iwrite echo from host data data
monitor module (mon) mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 205 the mcu executes the swi and pshh instructions when it enters monitor mode. the run command tells the mcu to execute the pulh and rti instru ctions. before sending th e run command, the host can modify the stacked cpu registers to prepare to run the host program. the readsp command returns the incremented stack pointer value, sp + 1. the high and low bytes of the program counter are at addresses sp + 5 and sp + 6. figure 17-17. stack pointer at monitor mode entry table 17-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns incremented stack pointer value (sp + 1) in high-byte:low-byte order opcode $0c command sequence table 17-8. run (run user program) command description executes pulh and rti instructions operand none data returned none opcode $28 command sequence readsp readsp echo from host sp return sp high low run run echo from host condition code register accumulator low byte of index register high byte of program counter low byte of program counter sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp sp + 6 high byte of index register sp + 7
development support mc68hc908qb8 data sheet, rev. 1 206 freescale semiconductor 17.3.2 security a security feature discourages unauthorized reading of flash locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locations $fff6?$fffd contain user-defined data. note do not leave locations $fff6?$fffd bl ank. for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the powe r-on reset for the host to send the eight security bytes on pin pta0. if the received bytes match those at locations $fff6?$fffd, the host bypasses the security feature and can read all flash locations and execute code from flash. security remains bypassed until a power-on reset occurs. if the reset wa s not a power-on reset, security remains bypassed and security code entry is not required. see figure 17-18 . upon power-on reset, if the received bytes of the security code do not match the data at locations $fff6?$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading a flash location returns an invalid value and trying to execute code from flash causes an illegal address reset. after receiving the eight secu rity bytes from the host, the mcu transmits a break character, signifying that it is ready to receive a command. note the mcu does not transmit a break char acter until after the host sends the eight security bytes. figure 17-18. monitor mode entry timing to determine whether the security code entered is correct, check to see if bit 6 of ram address $80 is set. if it is, then the correct security code has been entered and flash can be accessed. if the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. after failing the securi ty sequence, the flash module can also be mass erased by executing an erase routine that was downl oaded into internal ram. the mass erase operation clears the security code locations so that all eight security bytes become $ff (blank). byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pa0 rst v dd 4096 + 32 cgmxclk cycles 1 3 1 1 2 1 break notes: 2 = data return delay, approximately 2 bit times 3 = wait 1 bit time before sending next byte 3 from host from mcu 1 = echo delay, approximately 2 bit times 4 4 = wait until clock is stable and monitor runs
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 207 chapter 18 electrical specifications 18.1 introduction this section contains electrical and timing specifications. 18.2 absolute maximum ratings maximum ratings are the extreme limits to which t he microcontroller unit (mcu) can be exposed without permanently damaging it. note this device is not guaranteed to operate properly at the maximum ratings. refer to 18.5 5-v dc electrical characteristics and 18.8 3-v dc electrical characteristics for guaranteed operating conditions. note this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields ; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd .) characteristic (1) 1. voltages references to v ss . symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage v in v ss ?0.3 to v dd +0.3 v mode entry voltage, irq pin v tst v ss ?0.3 to +9.1 v maximum current per pin excluding pta0?pta5, v dd , and v ss i15ma maximum current for pins pta0?pta5 i pta0? i pta5 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma
electrical specifications mc68hc908qb8 data sheet, rev. 1 208 freescale semiconductor 18.3 functional operating range 18.4 thermal characteristics characteristic sy mbol value unit temperature code operating temperature range t a (t l to t h ) ? 40 to +125 ? 40 to +105 ? 40 to +85 c m v c operating voltage range v dd 2.7 to 5.5 v ? characteristic symbol value unit thermal resistance 16-pin pdip 16-pin soic 16-pin tssop ja 76 90 133 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) 1. power dissipation is a function of temperature. p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k constant unique to the device . k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c) + p d 2 x ja w/ c average junction temperature t j t a + (p d x ja ) c maximum junction temperature t jm 150 c
5-v dc electrical characteristics mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 209 18.5 5-v dc electrical characteristics characteristic (1) 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol min typ (2) 2. typical values reflect average measurements at midpoint of voltage range, 25c only. typical values are for reference only and are not tested in production. max unit output high voltage i load = ?2.0 ma, all i/o pins i load = ?10.0 ma, all i/o pins i load = ?15.0 ma, pta0, pta1, pta3?pta5 only v oh v dd ?0.4 v dd ?1.5 v dd ?0.8 ? ? ? ? ? ? v maximum combined i oh (all i/o pins) i oht ??50ma output low voltage i load = 1.6 ma, all i/o pins i load = 10.0 ma, all i/o pins i load = 15.0 ma, pta0, pta1, pta3?pta5 only v ol ? ? ? ? ? ? 0.4 1.5 0.8 v maximum combined i ol (all i/o pins) i ohl ??50ma input high voltage pta0?pta5, ptb0?ptb7 v ih 0.7 x v dd ?v dd v input low voltage pta0?pta5, ptb0?ptb7 v il v ss ? 0.3 x v dd v input hysteresis (3) 3. values are based on characterizati on results, not tested in production. v hys 0.06 x v dd ??v dc injection current, all ports (4) 4. guaranteed by design, not tested in production. i inj ?2 ? +2 ma total dc current injection (sum of all i/o) (4) i injtot ?25 ? +25 ma ports hi-z leakage current i il ?1 0.1 +1 a capacitance ports (as input) (3) c in ??8pf por rearm voltage v por 750 ? ? mv por rise time ramp rate (3)(5) 5. if minimum v dd is not reached before the internal por reset is re leased, the lvi will hold the part in reset until minimum v dd is reached. r por 0.035 ? ? v/ms monitor mode entry voltage (3) v tst v dd + 2.5 ?9.1v pullup resistors (6) pta0?pta5, ptb0?ptb7 6. r pu is measured at v dd = 5.0 v. r pu 16 26 36 k ? pulldown resistors (7) pta0?pta5 7. r pd is measured at v dd = 5.0 v, pulldown resistors only available when kbix is enabled with kbixpol =1. r pd 16 26 36 k ? low-voltage inhibit reset, trip falling voltage v tripf 3.90 4.20 4.50 v low-voltage inhibit reset, trip rising voltage v tripr 4.00 4.30 4.60 v low-voltage inhibit reset/recover hysteresis v hys ? 100 ? mv
electrical specifications mc68hc908qb8 data sheet, rev. 1 210 freescale semiconductor 18.6 typical 5-v output drive characteristics figure 18-1. typical 5-volt output high voltage versus output high current (25 c) figure 18-2. typical 5-volt output low voltage versus output low current (25 c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 -30 -25 -20 -15 -10 -5 0 ioh ( ma ) vdd-voh (v) 5v pta 5v ptb 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 5 10 15 20 25 30 iol ( ma ) vol (v) 5v pta 5v ptb
5-v control timing mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 211 18.7 5-v control timing figure 18-3. rst and irq timing characteristic (1) 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h ; timing shown with respect to 20% v dd and 70% v ss , unless otherwise noted. symbol min max unit internal operating frequency f op (f bus ) ?8mhz internal clock period (1/f op )t cyc 125 ? ns rst input pulse width low (2) 2. values are based on characterizati on results, not tested in production. t rl 100 ? ns irq interrupt pulse width low (edge-triggered) (2) t ilih 100 ? ns irq interrupt pulse period (2) t ilil note (3) 3. the minimum period is the number of cycles it take s to execute the interrupt service routine plus 1 t cyc . ?t cyc rst irq t rl t ilih t ilil
electrical specifications mc68hc908qb8 data sheet, rev. 1 212 freescale semiconductor 18.8 3-v dc electrical characteristics characteristic (1) 1. v dd = 2.7 to 3.3 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol min typ (2) 2. typical values reflect average measurements at midpoint of voltage range, 25c only. typical values are for reference only and are not tested in production. max unit output high voltage i load = ?0.6 ma, all i/o pins i load = ?4.0 ma, all i/o pins i load = ?10.0 ma, pta0, pta1, pta3?pta5 only v oh v dd ?0.3 v dd ?1.0 v dd ?0.8 ? ? ? ? ? ? v maximum combined i oh (all i/o pins) i oht ??50ma output low voltage i load = 0.5 ma, all i/o pins i load = 6.0 ma, all i/o pins i load = 10.0 ma, pta0, pta1, pta3?pta5 only v ol ? ? ? ? ? ? 0.3 1.0 0.8 v maximum combined i ol (all i/o pins) i ohl ??50ma input high voltage pta0?pta5, ptb0?ptb7 v ih 0.7 x v dd ?v dd v input low voltage pta0?pta5, ptb0?ptb7 v il v ss ? 0.3 x v dd v input hysteresis (3) 3. values are based on characterizati on results, not tested in production. v hys 0.06 x v dd ?? v dc injection current, all ports (4) 4. guaranteed by design, not tested in production. i inj ?2 ? +2 ma total dc current injection (sum of all i/o) (4) i injtot ?25 ? +25 ma ports hi-z leakage current i il ?1 0.1 +1 a capacitance ports (as input) (3) c in ??8pf por rearm voltage v por 750 ? ? mv por rise time ramp rate (3)(5) 5. if minimum v dd is not reached before the internal por reset is re leased, the lvi will hold the part in reset until minimum v dd is reached. r por 0.035 ? ? v/ms monitor mode entry voltage (3) v tst v dd + 2.5 ? v dd + 4.0 v pullup resistors (6) pta0?pta5, ptb0?ptb7 6. r pu is measured at v dd = 3.0 v r pu 16 26 36 k ? pulldown resistors (7) pta0?pta5 7. r pd is measured at v dd = 3.0 v, pulldown resistors only available when kbix is enabled with kbixpol =1. r pd 16 26 36 k ? low-voltage inhibit reset, trip falling voltage v tripf 2.40 2.55 2.70 v low-voltage inhibit reset, trip rising voltage (6) v tripr 2.475 2.625 2.775 v low-voltage inhibit reset/recover hysteresis v hys ?75?mv
typical 3-v output drive characteristics mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 213 18.9 typical 3-v output drive characteristics figure 18-4. typical 3-volt output high voltage versus output high current (25 c) figure 18-5. typical 3-volt output low voltage versus output low current (25 c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -25 -20 -15 -10 -5 0 ioh ( ma ) vdd-voh (v) 3v pta 3v ptb 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 5 10 15 20 25 iol ( ma ) vol (v) 3v pta 3v ptb
electrical specifications mc68hc908qb8 data sheet, rev. 1 214 freescale semiconductor 18.10 3-v control timing figure 18-6. rst and irq timing characteristic (1) 1. v dd = 2.7 to 3.3 vdc, v ss = 0 vdc, t a = t l to t h ; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit internal operating frequency f op (f bus )? 4 mhz internal clock period (1/f op )t cyc 250 ? ns rst input pulse width low (2) 2. values are based on characterizati on results, not tested in production. t rl 200 ? ns irq interrupt pulse width low (edge-triggered) (2) t ilih 200 ? ns irq interrupt pulse period (2) t ilil note (3) 3. the minimum period is the number of cycles it take s to execute the interrupt service routine plus 1 t cyc . ?t cyc rst irq t rl t ilih t ilil
oscillator characteristics mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 215 18.11 oscillator characteristics characteristic symbol min typ max unit internal oscillator frequency (1) icfs1:icfs0 = 00 icfs1:icfs0 = 01 icfs1:icfs0 = 10 (not allowed if v dd <2.7 v) 1. bus frequency, f op , is oscillator frequency divided by 4. f intclk ? ? ? 4 8 12.8 ? ? ? mhz trim accuracy (2)(3) 2. factory trimmed to provided 12.8mhz accuracy requirement ( 5%, @25c) for forced monitor mode communication. user should trim in-circuit to obtain the most accura te internal oscillator frequency for his application. 3. values are based on characterizati on results, not tested in production. ? trim_acc ? 0.4 ? % deviation from trimme d internal oscillator (3)(4) 4, 8, 12.8mhz, v dd 10%, 0 to 70 c 4, 8, 12.8mhz, v dd 10%, ?40 to 125 c 4. deviation values assumes trimming in target application @ 25c and midpoint of voltage range, for example 5.0 v for 5 v 10% operation. ? int_trim ? ? 2 ? ? 5 % external rc oscillator frequency, rcclk (1)(3) f rcclk 2?10mhz external clock reference frequencyy (1)(5)(6) v dd 4.5v v dd < 4.5v 5. no more than 10% duty cycle deviation from 50%. 6. when external oscillator clock is grea ter than 1mhz, ecfs1:ecfs0 must be 00 or 01 f oscxclk dc dc ?32 16 mhz rc oscillator external resistor (3) v dd = 5 v v dd = 3 v r ext see figure 18-7 see figure 18-8 ? crystal frequency, xtalclk (1)(7)(8) ecfs1:ecfs0 = 00 ( v dd 4.5 v) ecfs1:ecfs0 = 00 ecfs1:ecfs0 = 01 ecfs1:ecfs0 = 10 7. use fundamental mode only, do not use overtone crystals or overtone ceramic resonators 8. due to variations in electrical properties of extern al components such as, esr and load capacitance, operation above 16 mhz is not guaranteed for all crystals or ceramic resonator s. operation above 16 mhz requires that a negative resis- tance margin (nrm) characterization and component optimizatio n be performed by the crystal or ceramic resonator vendor for every different type of crystal or ceramic resonator whic h will be used. this characterization and optimization must be performed at the extremes of voltage and temperature which wi ll be applied to the microcontroller in the application. the nrm must meet or exceed 10x the ma ximum esr of the crystal or cerami c resonator for acceptable performance. f oscxclk 8 8 1 30 ? 32 16 8 100 mhz mhz mhz khz ecfs1:ecfs0 = 00 (9) feedback bias resistor crystal load capacitance (10) crystal capacitors (10) 9. do not use damping resistor when ecfs1:ecfs0 = 00 or 10 10. consult crystal vendor data sheet. r b c l c 1 ,c 2 ? ? ? 1 20 (2 x c l ) ? 5pf ? ? ? m ? pf pf ecfs1:ecfs0 = 01 (9) crystal series damping resistor f oscxclk = 1 mhz f oscxclk = 4 mhz f oscxclk = 8 mhz feedback bias resistor crystal load capacitance (10) crystal capacitors (10) r s r b c l c 1 ,c 2 ? ? ? ? ? ? 20 10 0 5 18 (2 x c l ) ?10 pf ? ? ? ? ? ? k ? k ? k ? m ? pf pf awu module internal rc oscillator frequency f intrc ? 32 ? khz
electrical specifications mc68hc908qb8 data sheet, rev. 1 216 freescale semiconductor figure 18-7. rc versus frequency (5 volts @ 25 c) figure 18-8. rc versus frequency (3 volts @ 25 c) 5v 25 o c 0 2 4 6 8 10 12 0 102030405060 r ext (k ohms) rc frequency, f rcclk (mhz) 3v 25 o c 0 2 4 6 8 10 12 0 102030405060 r ext (k ohms) rc frequency, f rcclk (mhz)
supply current characteristics mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 217 18.12 supply current characteristics characteristic (1) 1. v ss = 0 vdc, t a = t l to t h , unless otherwise noted. voltage bus frequency (mhz) symbol typ (2) 2. typical values reflect average measurements at midpoint of voltage range, 25c only. typical values are for reference only and are not tested in production. max unit run mode v dd supply current (3) 3. run (operating) i dd measured using trimmed internal oscillator, adc of f, all modules enabled. all pins configured as inputs and tied to 0.2 v from rail. 5.0 3.0 3.2 3.2 ri dd 7.25 3.1 8.5 3.8 ma wait mode v dd supply current (4) 4. wait i dd measured using trimmed internal oscillator, adc off, al l modules enabled. all pins configured as inputs and tied to 0.2 v from rail. 5.0 3.0 3.2 3.2 wi dd 1.0 0.67 1.5 1.0 ma stop mode v dd supply current (5) ?40 to 85 c ?40 to 105 c ?40 to 125 c 25 c with auto wake-up enabled (6) incremental current with lvi enabled 5. stop i dd measured with all pins configured as in puts and tied to 0.2 v from rail. 6. values are based on characterizati on results, not tested in production. 5.0 si dd 0.26 ? ? 12 125 1.0 2.0 5.0 ? ? a stop mode v dd supply current (4) ?40 to 85 c ?40 to 105 c ?40 to 125 c 25 c with auto wake-up enabled (6) incremental current with lvi enabled 3.0 0.23 ? ? 2 100 0.8 1.0 4.0 ? ? a
electrical specifications mc68hc908qb8 data sheet, rev. 1 218 freescale semiconductor figure 18-9. typical 5-volt run current versus bus frequency (25c) figure 18-10. typical 3-volt run current versus bus frequency (25c) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0123456789 bus frequency (mhz) idd internal osc (no a/d, esci, spi) internal osc all modules enabled crystal (no a/d) crystal all modules enabled external reference no a/d external reference all modules enabled 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 012345 bus frequency (mhz) idd (ma) internal osc (no a/d, esci, spi) internal osc all modules enabled crystal (no a/d) crystal all modules enabled
adc10 characteristics mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 219 18.13 adc10 characteristics characteristic conditions symbol min typ (1) max unit comment supply voltage absolute v dd 2.7 ? 5.5 v supply current adlpc = 1 adlsmp = 1 adco = 1 v dd < 3.3 v (3.0 v typ) i dd (2) ?55? a v dd < 5.5 v (5.0 v typ) ? 75 ? supply current adlpc = 1 adlsmp = 0 adco = 1 v dd < 3.3 v (3.0 v typ) i dd (2) ? 120 ? a v dd < 5.5 v (5.0 v typ) ? 175 ? supply current adlpc = 0 adlsmp = 1 adco = 1 v dd < 3.3 v (3.0 v typ) i dd (2) ? 140 ? a v dd < 5.5 v (5.0 v typ) ? 180 ? supply current adlpc = 0 adlsmp = 0 adco = 1 v dd < 3.3 v (3.0 v typ) i dd (2) ? 340 ? a v dd < 5.5 v (5.0 v typ) ? 440 615 adc internal clock high speed (adlpc = 0) f adck 0.40 (3) ?2.00 mhz t adck = 1/f adck low power (adlpc = 1) 0.40 (3) ?1.00 conversion time (4) 10-bit mode short sample (adlsmp = 0) t adc 19 19 21 t adck cycles long sample (adlsmp = 1) 39 39 41 conversion time (4) 8-bit mode short sample (adlsmp = 0) t adc 16 16 18 t adck cycles long sample (adlsmp = 1) 36 36 38 sample time short sample (adlsmp = 0) t ads 444 t adck cycles long sample (adlsmp = 1) 24 24 24 input voltage v adin v ss ?v dd v input capacitance c adin ? 7 10 pf not tested input impedance r adin ?515 k ? not tested analog source impedance r as ??10 k ? external to mcu ideal resolution (1 lsb) 10-bit mode res 1.758 5 5.371 mv v refh /2 n 8-bit mode 7.031 20 21.48 total unadjusted error 10-bit mode e tue 0 1.5 2.5 lsb includes quantization 8-bit mode 0 0.7 1.0 differential non-linearity 10-bit mode dnl 0 0.5 ? lsb 8-bit mode 0 0.3 ? monotonicity and no-missing-codes guaranteed ? continued on next page
electrical specifications mc68hc908qb8 data sheet, rev. 1 220 freescale semiconductor integral non-linearity 10-bit mode inl 0 0.5 ? lsb 8-bit mode 0 0.3 ? zero-scale error 10-bit mode e zs 0 0.5 ? lsb v adin = v ss 8-bit mode 0 0.3 ? full-scale error 10-bit mode e fs 0 0.5 ? lsb v adin = v dd 8-bit mode 0 0.3 ? quantization error 10-bit mode e q ?? 0.5 lsb 8-bit mode is not truncated 8-bit mode ? ? 0.5 input leakage error 10-bit mode e il 0 0.2 5 lsb pad leakage (5) * r as 8-bit mode 0 0.1 1.2 bandgap voltage (3)(6) v bg 1.17 1.245 1.32 v 1. typical values assume v dd = 5.0 v, temperature = 25c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. incremental i dd added to mcu mode current. 3. values are based on characterizati on results, not tested in production. 4. reference the adc modul e specification for more information on calculating conversion times. 5. based on typical input pad leakage current. 6. lvi must be enabled, (lvipwrd = 0, in config1). voltage input to adch4:0 = $1a, an adc conversion on this channel allows user to determine supply voltage. characteristic conditions symbol min typ (1) max unit comment
5.0-volt spi characteristics mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 221 18.14 5.0-volt spi characteristics diagram number (1) 1. numbers refer to dimensions in figure 18-11 and figure 18-12 . characteristic (2) 2. all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. symbol min max unit operating frequency master slave f op(m) f op(s) f op /128 dc f op /2 f op mhz mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 ? t cyc t cyc 2 enable lead time t lead(s) 1?t cyc 3 enable lag time t lag(s) 1?t cyc 4 clock (spsck) high time master slave t sckh(m) t sckh(s) t cyc ?25 1/2 t cyc ?25 64 t cyc ? ns ns 5 clock (spsck) low time master slave t sckl(m) t sckl(s) t cyc ?25 1/2 t cyc ?25 64 t cyc ? ns ns 6 data setup time (inputs) master slave t su(m) t su(s) 30 30 ? ? ns ns 7 data hold time (inputs) master slave t h(m) t h(s) 30 30 ? ? ns ns 8 access time, slave (3) cpha = 0 cpha = 1 3. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 40 40 ns ns 9 disable time, slave (4) 4. hold time to high-impedance state t dis(s) ?40ns 10 data valid time, after enable edge master slave (5) 5. with 100 pf on all spi pins t v(m) t v(s) ? ? 50 50 ns ns 11 data hold time, outputs, after enable edge master slave t ho(m) t ho(s) 0 0 ? ? ns ns
electrical specifications mc68hc908qb8 data sheet, rev. 1 222 freescale semiconductor 18.15 3.0-volt spi characteristics diagram number (1) 1. numbers refer to dimensions in figure 18-11 and figure 18-12 . characteristic (2) 2. all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. symbol min max unit operating frequency master slave f op(m) f op(s) f op /128 dc f op /2 f op mhz mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 ? t cyc t cyc 2 enable lead time t lead(s) 1?t cyc 3 enable lag time t lag(s) 1?t cyc 4 clock (spsck) high time master slave t sckh(m) t sckh(s) t cyc ?35 1/2 t cyc ?35 64 t cyc ? ns ns 5 clock (spsck) low time master slave t sckl(m) t sckl(s) t cyc ?35 1/2 t cyc ?35 64 t cyc ? ns ns 6 data setup time (inputs) master slave t su(m) t su(s) 40 40 ? ? ns ns 7 data hold time (inputs) master slave t h(m) t h(s) 40 40 ? ? ns ns 8 access time, slave (3) cpha = 0 cpha = 1 3. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 50 50 ns ns 9 disable time, slave (4) 4. hold time to high-impedance state t dis(s) ?50ns 10 data valid time, after enable edge master slave (5) 5. with 100 pf on all spi pins t v(m) t v(s) ? ? 60 60 ns ns 11 data hold time, outputs, after enable edge master slave t ho(m) t ho(s) 0 0 ? ? ns ns
3.0-volt spi characteristics mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 223 figure 18-11. spi master timing note note: this first clock edge is generated internally, but is not seen at the spsck pin. ss pin of master held high msb in ss input spsck output spsck output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 11 10 11 7 6 note note: this last clock edge is generated inte rnally, but is not seen at the spsck pin. ss pin of master held high msb in ss input spsck output spsck output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) cpol = 0 cpol = 1 cpol = 0 cpol = 1
electrical specifications mc68hc908qb8 data sheet, rev. 1 224 freescale semiconductor figure 18-12. spi slave timing note: not defined but normally msb of character just received slave ss input spsck input spsck input miso input mosi output 4 5 5 1 4 msb in bits 6?1 8 6 10 5 11 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out note: not defined but normally lsb of character previ ously transmitted slave ss input spsck input spsck input miso output mosi input 4 5 5 1 4 msb in bits 6?1 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11 cpol = 0 cpol = 1 cpol = 0 cpol = 1
timer interface module characteristics mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 225 18.16 timer interface module characteristics figure 18-13. timer input timing characteristic symbol min max unit timer input capture pulse width (1) 1. values are based on characterizati on results, not tested in production. t th, t tl 2?t cyc timer input capture period t tltl note (2) 2. the minimum period is the number of cycles it take s to execute the interrupt service routine plus 1 t cyc . ?t cyc timer input clock pulse width (1) t tcl , t tch t cyc + 5 ? ns input capture rising edge input capture falling edge input capture both edges t th t tl t tltl t tltl t tltl t tl t th tclk t tcl t tch
electrical specifications mc68hc908qb8 data sheet, rev. 1 226 freescale semiconductor 18.17 memory characteristics characteristic symbol min typ (1) 1. typical values are for reference only and are not tested in production. max unit ram data retention voltage (2) 2. values are based on characterizati on results, not tested in production. v rdr 1.3 ? ? v flash program bus clock frequency ? 1 ? ? mhz flash pgm/erase supply voltage (v dd )v pgm/erase 2.7 ? 5.5 v flash read bus clock frequency f read (3) 3. f read is defined as the frequency range for which the flash memory can be read. 0?8 mhz flash page erase time <1 k cycles >1 k cycles t erase 0.9 3.6 1 4 1.1 5.5 ms flash mass erase time t merase 4??ms flash pgm/erase to hven setup time t nvs 10 ? ? s flash high-voltage hold time t nvh 5?? s flash high-voltage hold time (mass erase) t nvhl 100 ? ? s flash program hold time t pgs 5?? s flash program time t prog 30 ? 40 s flash return to read time t rcv (4) 4. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clear- ing hven to 0. 1?? s flash cumulative program hv period t hv (5) 5. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog x 32) t hv maximum. ?? 4ms flash endurance (6) 6. typical endurance was evaluated for this product family. for additional information on how freescale semiconductor defines typical endurance , please refer to engineering bulletin eb619. ? 10 k 100 k ? cycles flash data retention time (7) 7. typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25c using the arrhenius equation. for additional information on how freescale semiconductor defines typical data retention , please refer to engineering bulletin eb618. ? 15 100 ? years
mc68hc908qb8 data sheet, rev. 1 freescale semiconductor 227 chapter 19 ordering information and mechanical specifications 19.1 introduction this section contains order numbers for th e mc68hc908qb8, MC68HC908QB4, and mc68hc908qy8. dimensions are given for: 16-pin pdip 16-pin soic 16-pin thin shrink small outline packages (tssop) 19.2 mc order numbers figure 19-1. device numbering system 19.3 package dimensions refer to the following pages fo r detailed package dimensions. table 19-1. mc order numbers mc order number package mc908qb8 16-pins pdip, soic, and tssop mc908qb4 mc908qy8 temperature and package designators: c = ?40c to +85c v = ?40c to +105c m = ?40c to +125c p = plastic dual in-line package (pdip) dw = small outline integrated circuit package (soic) dt = thin shrink small outline package (tssop) e = lead free m c 9 0 8 q b 8 x x x e family indicates lead-free package package designator temperature range

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